JPS6184040A - 樹脂封止形半導体メモリ装置 - Google Patents
樹脂封止形半導体メモリ装置Info
- Publication number
- JPS6184040A JPS6184040A JP20502484A JP20502484A JPS6184040A JP S6184040 A JPS6184040 A JP S6184040A JP 20502484 A JP20502484 A JP 20502484A JP 20502484 A JP20502484 A JP 20502484A JP S6184040 A JPS6184040 A JP S6184040A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- memory array
- array forming
- forming part
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 229920005989 resin Polymers 0.000 title claims abstract description 25
- 239000011347 resin Substances 0.000 title claims abstract description 25
- 239000004065 semiconductor Substances 0.000 title claims abstract description 11
- 230000015654 memory Effects 0.000 claims abstract description 28
- 238000007789 sealing Methods 0.000 abstract description 22
- 229920003002 synthetic resin Polymers 0.000 abstract description 5
- 239000000057 synthetic resin Substances 0.000 abstract description 5
- 239000012535 impurity Substances 0.000 abstract description 4
- 230000002542 deteriorative effect Effects 0.000 abstract description 3
- 238000000034 method Methods 0.000 abstract 1
- 238000002161 passivation Methods 0.000 description 8
- 230000007774 longterm Effects 0.000 description 5
- 230000014759 maintenance of location Effects 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 238000000465 moulding Methods 0.000 description 4
- 239000004593 Epoxy Substances 0.000 description 3
- 239000000919 ceramic Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000008595 infiltration Effects 0.000 description 1
- 238000001764 infiltration Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000004793 poor memory Effects 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3135—Double encapsulation or coating and encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20502484A JPS6184040A (ja) | 1984-09-29 | 1984-09-29 | 樹脂封止形半導体メモリ装置 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20502484A JPS6184040A (ja) | 1984-09-29 | 1984-09-29 | 樹脂封止形半導体メモリ装置 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6184040A true JPS6184040A (ja) | 1986-04-28 |
| JPH0321090B2 JPH0321090B2 (enrdf_load_stackoverflow) | 1991-03-20 |
Family
ID=16500178
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20502484A Granted JPS6184040A (ja) | 1984-09-29 | 1984-09-29 | 樹脂封止形半導体メモリ装置 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6184040A (enrdf_load_stackoverflow) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5988850A (ja) * | 1982-11-12 | 1984-05-22 | Toshiba Corp | 集積回路装置 |
-
1984
- 1984-09-29 JP JP20502484A patent/JPS6184040A/ja active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5988850A (ja) * | 1982-11-12 | 1984-05-22 | Toshiba Corp | 集積回路装置 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0321090B2 (enrdf_load_stackoverflow) | 1991-03-20 |
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