Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba CorpfiledCriticalToshiba Corp
Priority to JP20483084ApriorityCriticalpatent/JPS6182236A/ja
Publication of JPS6182236ApublicationCriticalpatent/JPS6182236A/ja
Publication of JPH0518137B2publicationCriticalpatent/JPH0518137B2/ja
G06F9/00—Arrangements for program control, e.g. control units
G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
G06F9/22—Microcontrol or microprogram arrangements
G06F9/26—Address formation of the next micro-instruction ; Microprogram storage or retrieval arrangements
G06F9/262—Arrangements for next microinstruction selection
G06F9/268—Microinstruction selection not based on processing results, e.g. interrupt, patch, first cycle store, diagnostic programs
Multi-processor system for selecting a processor which has successfully written it's ID into write-once register after system reset as the boot-strap processor
Multiprocessor system having a plurality of control programs stored in a continuous range of addresses of a common memory and having identification registers each corresponding to a processor and containing data used in deriving a starting address of a CPU-linked interrupt handler program to be executed by the corresponding processor