JPS6181010A - Btl circuit - Google Patents

Abstract

PURPOSE:To prevent the breakdown of a transistor (TR) by providing a protecting circuit, which cuts off the TR not to flow an overcurrent to the TR when an output terminal is grounded, in an output circuit of a power amplifier or the like. CONSTITUTION:The output of a detecting circuit 20 is connected to an input terminal 201 of a comparing circuit 26 through a level shifting circuit 24, and the output of a detecting circuit 22 is connected to an input terminal 101 of a comparing circuit 25 through a level shifting circuit 23. If the output of the comparing circuit 25 or 26 goes to the high level, a control circuit 27 is operated to cut off a driving circuit 16 or 17, and TRs Q11-Q14 are turned off. Outputs of detecting circuits 19-22 go to the high level when it is detected that a difference is generated between collector currents of TRs Q11 and Q14 or TRs Q12 and Q13.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a BTL circuit (Ba1lanced Tranform) used as an output circuit of a power amplifier or the like.
erLegs circuit).

[Conventional technology]

FIG. 6 is a circuit diagram showing an example of a conventional BTL circuit.

NPN) transistor (hereinafter referred to as NPN) transistor.

PNP) Both transistors are simply called transistors ψQ
1, Q2 and transistors Q3 and Q4 are connected in series to form a push-pull circuit, which is connected between power supply terminal 5 and ground. And transistor Q1. The pace of Q2 is driven by the input signal from the input terminal 1 via the drive circuit 6, while the pace of the transistors Qs and Q4 is driven by the negative phase input signal from the input terminal 2 via the υ drive circuit 7. , output terminal 3,
It also outputs 4.

In the figure, 8 is a load.

[Problem that the invention seeks to solve]

In the conventional BTL circuit shown in Fig. 6, when the transistor Q□+Q4 is in the operating state, the output terminal 3 is grounded, and when the transistors Qs and Qz are in the operating state, the output terminal 4 is grounded. In the former case, an overcurrent flows through the transistor Q1, and in the latter case, an overcurrent flows through the transistor Q3, resulting in destruction of the transistor Q□+Q3.

The purpose of the present invention is to solve such problems by
The BTL circuit of the present invention provides a BTL circuit equipped with a protection circuit that prevents and interrupts overcurrent from flowing into the transistor even when either one of the output terminals is grounded. The second transistors are connected in series and the middle point is the first transistor.
a first push-pull circuit configured as an output terminal of;
Third. a second push-pull circuit in which fourth transistors are connected in series and whose midpoint is configured as a second output terminal; The first one drives the inputs of the second sheep pull circuit in opposite phases. and a second drive circuit. The first .
Second. a third and fourth detection circuit, a first comparison circuit that compares the output of the first detection circuit and the output of the fourth detection circuit via the first level shift circuit;
a second comparison circuit that compares the output of the detection circuit and the output of the second detection circuit via the second level shift circuit; the output of the second comparison circuit and the output of the first comparison circuit; As input, the first . and a control circuit that controls the second drive circuit.

[Effect]

FIG. 1 is a block diagram showing the basic configuration of the BTL circuit of the present invention.

The BTL circuit of the present invention has the following features: 1. second transistor Ql
l l A first push-pull circuit in which Q12 are connected in series and whose midpoint is configured as the first output terminal 13;
．． A second push-pull circuit in which fourth transistors Q1!1Q14 are connected in series and whose middle point is configured as the second output terminal 14; + Qtz and Q engineering 3
The 1st. Second
In the BTL circuit including first and second drive circuits 16 and 17, respectively. 2nd degree third and fourth transistors (ht
~Q□4 base-emitter voltage Vagt-Detected 1st. Second. Third and fourth detection circuits 19 to 22, the output of the first detection circuit 19 and the first level shift circuit 2
A first comparison circuit 25 with a differential configuration that compares the output of the fourth detection circuit 22 via the third detection circuit 21 and a second detection via the output of the third detection circuit 21 and the second level shift circuit 24. A second comparator circuit 26 with a differential configuration that compares the outputs of the circuit 20
, the output of the second comparison circuit 26 and the first comparison circuit 25
The first output is the input. The conditions for the operation of the control circuit 27 that controls the second drive circuit 16 and 17 are that it operates when the output of the comparison circuit 25 or 26 becomes a high level, and stops the operation of the drive circuit 16 or 17. From the action K, the transistors Q□1-Q, 4 are interrupted. Furthermore, the detection circuits 19 to 22 are connected to transistors Q□ and Q4 or Qtz. , 3 collector current IC
When detecting that there is a difference between I to IC4, a high level is output.

Next, the basic operation of the circuit shown in FIG. 1 will be explained.

The output of the detection circuit 19 is V□, the output voltage of the detection circuit 2o is V2%, the output of the ratio detection 21 is Va, the output voltage of the detection circuit 22 is V4, the level shift circuit 23°240, the level shift voltage is VL1, the comparison circuit 250 Input terminal 101.102
The voltage at the input terminals 201 and 202 of the comparator circuit 26 is set to v2゜1゜v202.
Also, the output of the detection circuit 22 is connected to the input terminal 201 of the comparison circuit 26 and the latter to the input terminal 101 of the comparison circuit 25 via the level shift circuit 23, so that
. 0. v2゜□ and V□. 8゜V2O2 is vl,, (Vzot > xva <v2> -vL
・-・・・(i)Vro2 (V2O2) -V
l (V3) --(2). The collector currents of transistors Qll to Q, respectively are ICI
*IC2* IC3s IC4, during normal operation; Rector current Ic and I C4s or IC2 and I
(If J is equal to V, v4 (v2) Akebono V, (V, ), then from the relationship between equations (1) and (2), vlOl (V2O
1) The following relationship holds true: <V1O2(V2O2) --<3). In the state of equation (3), the outputs of the comparison circuits 25 and 26 are at the a-low level, and therefore the control circuit 27 is also in a cutoff state.

Next, the collector current Ic and IC4 or IC2 and IC8
When there is a difference between ICI>IC4 or Icx>Icz, the output voltage V or v3 of the detection circuit 19 or 21 becomes Vl(V3)<V4(V2)-Vt,
--(4), Vlol (V2O1) > Vlo2(V2O2)
...The relationship (5) holds true. If the circuit configuration is such that the outputs of the comparator circuit 25 and the comparator circuit 26 become high level when the state of equation (5) is reached, the control circuit 2
7 operates, and the drive circuits 16, 171 &:L are interrupted, thereby causing the transistors Qll to Q□4 to be interrupted.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 is a circuit diagram showing one embodiment of the present invention.

In FIG. 2, transistors Q1° and Ql. 2゜Q
sos and Q104 + Qsos and Qlog and Q10
? and Q108 are Darlington connected and resistor R2p R
3y R5+ R7 and constant current source 28.29,
Configure an output circuit with a BTL configuration. Also, transistor Q
111~Q□14 resistance R1* R4r R6# Rs
""' Rsx constitutes a detection circuit, which includes diodes DI and D2 as a level shift circuit. And transistors Q1□5 to Q11. A differential comparator circuit is made up of constant current sources 30, 31, and resistors R1, R16, and a control circuit is made up of transistors Q119 to Q122 and resistors R17 to R2.
1091Q□1° constitutes a drive circuit. Of the transistors, Q□. 3゜QIO? + Qll! l
"Qtls is PNP) transistor, others are NPN)
The transistor 32 is a ground terminal. Here, the diodes D and D2 each have their forward voltages V D 1
and VD2, transistors Q1□6 and Q018
The pace potential of transistors Q1□5 and Q1□7 is lowered across vDl and VD.

Next, the operation of this embodiment will be explained with reference to the explanatory diagrams of the operation shown in FIGS. 3, 4, and 5.

Since the output circuit has a push-pull configuration, during normal operation, the transistor Q1゜z r Qtos is in the on state, and a current as shown in Fig. 3 flows, and the transistor Q1
04 + Ql. 6 is on, a current I' in FIG. 3 flows. Transistor Q1゜2. Ql. 8 is on, transistor Q0°4 + Q106 is off, or transistor Qroz + Q□. 8 is off,
The transistors Q104+Q□o6 are switched on by applying signals of opposite phases to the input terminals 11 and 12 from the outside, and switching is performed in accordance with the signals.

Also, during the on operation, the transistor Q□. 1Q Yu.

, and transistors Q1゜4+Q□o6 have the same emitter area, DC current amplification factor hrg, etc., then transistors Q1oz, Qtoa + Q104, and Qsoe
The base-emitter voltage Milli (s VB
ψ K becomes equal.

Therefore, the voltage between the output terminal 13 and the output terminal 13 of the detection transistor Q1□, which constitutes the detection circuit connected to the transistor Q1゜2, and the transistor voltage. The voltage between the pace and ground of the detection transistor Q1□4 constituting the detection circuit connected to Q8 is equal, and the voltage between the transistor Q8゜6
A detection transistor Q forming a detection circuit connected to
The voltage between the output terminal 14 and the output terminal 14 becomes equal to the voltage between the base of the detection transistor Q1□2, which constitutes the detection circuit connected to the transistor Q8゜4, and the ground. At this time, the collector current ICI□ flowing through the detection transistor Q111 is as follows: %= 1+77 t=
Saq East).

+ I(11(1+1/hrztt)J...
・(6) However, K: Boltzmann constant, T: absolute temperature,
q: electron charge, hrzlt') transistor Q11
, DC current amplification of EE, I. □, :Transistor Q1□
Reverse saturation current s vBE2 ')' transistor Q□. , the base-emitter curve voltage.

Calculating ICI□ from equation (6), T vBE2--1゜Similarly, the collector current IC flowing through the detection transistor Q1□4 is, however, shFE□: DC current amplification of transistor Q0.4 rate s l514') transistor Q□□4
Reverse saturated N flow, VB1@: )5 transistor Q1o
s O base-emitter voltage.

Here, the collector current I flowing through the transistor Q1゜
C2 and transistor Q□. Collector current flowing through IC
If equal to 8, VDl2- VnE@ fk b,
If the vll·h, ridge and emitter areas of Torafuji 3 Yo Qllll and Q114 are equal, and if R1°=R1, then Equation (7).

(τ) formula becomes She C□1　””　IC14.

Therefore, the input voltage of the differential comparator circuit, that is, the transistor Q? 1Q1□80 base potential VB171VB
1g, the forward voltage of diode D□+D2 is VDl,
vD, so vB1s=vcc IC14×R11−vD2
°°---(8)VB17=VCCICIIXRI
O--(9).

Here, IC□□-Icm4. Since R1° - R1□, % From equations (8) and (9), VBlg<VB□7 due to the difference in forward voltage VD2 of diode D2, transistor Q11a is in the on state, and transistor Q1
□7 is in the off state, and since no voltage drop occurs in the resistor R11, the transistors Q12□ and Q forming the control circuit
Yu 2. does not operate, and the output circuit maintains normal operation.

Conversely, when the output transistor Q1as + Q1G4 is in the operating state, the detection transistor Q112 + Ql
□ performs the same operation as above.

Next, consider the case where either the output terminal 13 or the output terminal 14 is grounded as shown in FIGS. 4 and 5.

First, as shown in FIG. 4, when the output terminal 13 is grounded, the collector '1K of the transistor Q102 and the current IC2
Icz = Vcc / rscQto2- (9) where rscQto2-. 2 is the saturation resistance of transistor Q1゜2.

A current flows.

Here, when the output terminal 13 is grounded, the output terminal 131
The voltage V□3 generated by C increases the ground impedance by R8%.
If the current flowing through the ground point is 2, then Vla −R8X
I2...A voltage of αQ is generated. Hence, the transistor. Collector current IC11 also flows through 108, and its current value is IC2-
IC8') Ics -1cx II.

Therefore, since Ics < IC2, it is a transistor! : ') Vnzz > Vnr, s.

Therefore, the collector current ICII of the transistor Q1□1 for detecting vBE of the transistor Q1°2 becomes R1 (continued on next page).

In addition, the collector current IC14 of the VBE detection transistor Q1□4 at the mouth of the transistor Q1° is TVBts 1n IC+4 ”□ Here, if R1=R and 1811-1514, VBIC2>Vnzs, so ICII>
The relationship of IC14 holds true.

Next, the pace potential v1111 + VBI? of the transistor Q□1B 1 Ql□7 of the comparison circuit? is the formula (8),
(9) Formula! VBIII” vcc IC14
X R11VO2””...(8) VDI7 = VCC
ICII
-eA, VBQI□7<VIIQI□, the transistor Q1□8 is in the off state, the transistor Q1□7 is in the on state, and the resistor R□. Since a voltage drop occurs, the transistor Q and H+ that make up the control circuit
QB2 operates, transistor Q1゜2 p Qtog
By absorbing the pace drive current of
Yu. 8. Ql. It can protect against overcurrent damage of 8.

The above explanation describes the operation of the protection circuit when the transistor Q102 * Q1o6 is in the on state and the output terminal 13 is grounded.
Even when Qto4 is on and the output terminal 14 is grounded, the transistor Q1□2+Q□, 3°Qst
s + Qllg performs the same operation as above, and transistors Qsts + Q1□ constitute a control circuit.
.

is turned on and the transistor Q is turned on. 4+Q□. By absorbing the pace drive current of 6, the transistor Q0゜4゜Q
Engineering. 6 is cut off to prevent its destruction.

Next, when the output terminal 14 is grounded as shown in Figure 5,
Transistors Qxoz, Ql. If 8 is on,
In the collector current IC2 of the transistor Q102, R is the load impedance, and vcΣ(8AT)2 is the transistor Q□. 2 collector-emitter saturation voltage.

becomes.

Here, for IC2, if the current flowing to the ground point is 3, and the collector current of transistor Q1゜8 is ICII, then IC2
= Is + Ics −...(
A4 and Nasi, also XCSoI (J I3...
・(G) Therefore, IC2>IC8.

Therefore, as mentioned above, VBE2 > Vnia and b,
■. , t > IC14.

Here, since the relationship s IC2 > IC8 holds as described above, the input voltage of the comparator circuit with a differential configuration is VDI
Since 7<VDI8 and a difference occurs, the transistors Q12□, Q□2□Kao/L, which constitute the control circuit, and the output circuit are cut off to prevent destruction.

Also, the transistor Q1os + Qt. 4 is in the on state and the output terminal 13 is grounded, the same operation as above is performed, and the transistor Q)n forming the control circuit
* Qlzo is turned on, cutting off the output circuit and preventing damage.

As described above, according to this embodiment, the transistor Q□. 2 and Q 1
os or 1 Since the protection circuit operates when the transistor currents of the transistors Q10g and Q104 become unbalanced, there will be no malfunction even if the transistor is grounded with a resistor of several ohms.

Further, the unbalance ratio of the output transistor can be set by V□/R□□ (or VDI/R9) according to equation (6).

〔Effect of the invention〕

As described above in detail, the BTL circuit of the present invention has a protection circuit that cuts off overcurrent to the transistor when the output terminal configured as described above is grounded, so it is different from the conventional one. This has the effect that the transistor is not destroyed during the process.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing the basic configuration of the BTL circuit of the present invention, Fig. 2 is a circuit diagram showing an embodiment of the invention, and Figs. 3, 4, and 5 are explanatory diagrams of its operation. , FIG. 6 is a circuit diagram showing an example of a conventional BTL circuit. 11.12... Input terminal, 13.14...
...Output terminal, 15...Power terminal, 16.17
......Drive circuit, 18...Load, 19~
22...detection circuit, 23.24...level shift circuit, 25.26...comparison circuit, 2
7... Control circuit, 28-31... Constant current source, 32... Ground terminal, 101, 102
, 201, 202... input terminals of the comparison circuit,
D□, D2...Diode, R-ate...
...Resistance, Qll ~Q14! QIOI+
Qloz p Qsoa ~Qlo6* Q1os~Q
114・Q 11+1~Q122°−-NPN) transistor, Q103, Q1G? TQIIS-Qt
ts-...PNP) transistor. Su J Togan 3 Kuni Kayada times

Claims (1)

[Claims] A first push-pull circuit in which first and second transistors are connected in series and their midpoint is configured as a first output terminal, and a third and fourth transistor are connected in series and their midpoint is configured as a second output terminal. A BTL circuit including a second push-pull circuit configured as a terminal, and first and second drive circuits that drive inputs of the first and second push-pull circuits in opposite phases, respectively. , a first detecting base-emitter voltage of the second, third and fourth transistors.
, second, third and fourth detection circuits, and the output of the first detection circuit and the fourth level shift circuit.
a first comparison circuit that compares the outputs of the detection circuits; and a second comparison circuit that compares the outputs of the third detection circuit and the output of the second detection circuit via the second level shift circuit. , a control circuit that controls the first and second drive circuits by using the output of the second comparison circuit and the output of the first comparison circuit as inputs.