JPS6180914A - Controlling method of gate driving circuit - Google Patents

Abstract

PURPOSE:To control stably a titled circuit irrespective of whether the on-period and off-period of an MOS FET are long or short, by executing a gate driving control by using a D-FF, even in case an on-signal of the MOS FET used for an invertor of a PWM control is short. CONSTITUTION:When an on-off signal 15 of an FET becomes H and a clock 18 becomes H, an H output of a width of a one period portion is outputted from an AND circuit 20, and set to a gate driving circuit constituted of a flip- flop through a pulse transformer 22. On the contrary, when the signal 15 becomes L and the clock 18 becomes H, an H output is outputted from an AND circuit 21, the gate driving circuit of the FET is reset through a pulse transformer 23, and the FET is turned on during the time roughly corresponding to the signal 15. Even if the signal 15 is shorter than a time width of one period of the clock, when the clock becomes H, the FET can send out an on-driving signal from the gate driving circuit by a one period portion of the clock, and a malfunction can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a control method for a gate drive circuit of a MOS-FET, and is particularly suitable for a high-frequency MOSFET inverter for driving a motor.

[Background of the invention]

As a gate drive circuit for a MOS FET, for example, as shown in Hitachi Review Vol. 65 No. 4, page 39, there is a known one in which a signal from a control circuit is amplified using a photocoupler and a transistor.

There is also a method of setting and resetting a clip 1 flop circuit using a pulse lance as a gate drive circuit for a MOS PET with high-speed response. This type of gate drive circuit has a fast response, so it is a PWM (pulse width modulation) controlled MOS.
When applied to a FET inverter, control performance can be improved. However, no consideration was given to the operation of the gate drive circuit when the ON period of the MOSFET becomes very short.

[Purpose of the invention]

An object of the present invention is to provide a control method that allows a gate drive circuit to operate stably at all times regardless of the length of the on period and off period of a MOS FET.

[Summary of the invention]

The gist of the present invention is to prevent malfunction of the gate drive circuit by generating set and reset signals with constant value widths that are not affected by the length of the on/off period of the MOS FET.

[Embodiments of the invention]

FIG. 1 shows a gate drive circuit for a MOS FET and a control circuit for the gate drive circuit which is an embodiment of the present invention.

In the figure, 1 is a DC power supply, 2 and 3 are MOSFETs, and 4
．． 5 is a transistor, and 6 to 14 are resistors. Also, 1
5 is a MOS FET on/off signal input terminal, 16
．． 17 is a clip-flop circuit, 18 is a black pulse input terminal, 19 is an exclusive OR circuit M, 20.2
1 is an AND circuit, 22.23 is a pulse transformer, 24.
25 is MOS FET, 26 to 29 are resistors, 30.3
1 is an input terminal of a DC power supply.

In the PWN1 controlled in/verter, the on/off signal of the MOS FET may be very short.

That is, in FIG. 2, the modulated wave signal C that determines the fundamental frequency of the inverter output voltage is compared with the carrier wave signal H that determines the carrier frequency, and when the voltage levels match, the MOS
Performs FET switching. Since such a method is adopted, depending on the timing of the modulated wave signal C and the carrier wave signal H, the on/off periods of the MO8FET may become extremely short.

3 and 4 are operation explanatory diagrams of the embodiment of the present invention shown in FIG. 1. Figure 3 shows that when the ON period of the MOS FET is longer than one cycle of the clock pulse, the jg4 diagram shows M
FIG. 6 is an explanatory diagram of the operation when the ON period of OS FET is shorter than one period of the clock pulse. In FIG. 1, a high frequency clock pulse of, for example, 10 MHz and 8 degrees is input to the slip-flop circuits 116 and 17. Flip-flop circuit 16.17
is set and reset when the clock pulse changes from MO'' to '1''.

k! , In Figure 3, the MOS FET on and off signals are '
The clock pulse immediately after reaching l'' changes from 'O'' to 11''
The signal from the AND circuit 20 is output from the point in time when the value changes to . The width of the signal at this time is O, lμs for one cycle of the clock pulse. This signal causes pulse transformer 2
A signal is output from 2, and the gate drive circuit of the MOS FET turns on. Then t'vl OS F
When the ON/OFF signal of ET becomes 0'', the signal of the AND circuit 21 is output from the point at which the immediately following clock pulse changes from 0'' to 1.The width of the signal at this time is similarly the width of the clock pulse. This is 061 μs for one cycle. According to this signal, a signal is output from the pulse transformer 23 and the MO
The SFET gate drive circuit is turned off. In this way, since the output signal width of the AND circuits 20 and 21 is a constant value determined by the clock pulse, the MOSFET gate drive circuit operates stably.

If the ON period of the MOS FgT in Figure 4 is shorter than one cycle of the clock pulse, the AND circuit is activated only when the clock pulse changes from O'' to “L” while the MOSFET ON/OFF signal is “L”. 20 to 21 output signals having a constant value width as described above.

Therefore, the on/off signal of MOS FET is '1
If the clock pulse does not change from "0" to 'l#' during this period, the AND circuits 20 and 21 will not output any signals, so the gate drive circuit of the MOS FET will not operate, but for a short time of about 0.1 μs. Therefore, the performance of PWM control is not affected.

In this way, the circuit system shown in Figure 1 turns on the MOSFET,
Even when the OFF period becomes very short, stable ON and OFF signals with a constant value width can be sent to the gate drive circuit of the MOSFET, so malfunction of the gate interlocking circuit can be prevented.

〔Effect of the invention〕

According to the present invention, it is possible to send an on/off signal of a constant value width to the gate drive circuit regardless of the width of the on/off period of the MOSFET, so that malfunction of the gate drive circuit can be prevented.

[Brief explanation of the drawing]

Fig. 1 is a control circuit diagram of a MOSFET gate drive circuit and the gate drive circuit of the present invention, Fig. 2 is an explanatory diagram of PWM control, and Figs. 3 and 4 are explanatory diagrams of the operation of the circuit of Fig. 1. . 2.3...MOS FET516.17...Clip Fold /m

Claims (1)

[Claims] 1. A method for controlling a gate drive circuit which forward biases a gate terminal of a MOSFET to turn it on and removes the bias to turn it off, comprising: inputting an on/off signal for controlling the MOSFET;
An output signal of a first flip-flop circuit that operates with a clock pulse is input, an output signal of a second flip-flop circuit that operates with the clock pulse, an output signal of the first flip-flop circuit, and the output signal of the first flip-flop circuit are input. The gate drive circuit of the MOSFET is turned on by the AND signal of the exclusive OR signal with the output signal of the second flip-flop circuit, and the exclusive OR signal and the output signal of the second flip-flop circuit are turned on. A method of controlling a gate drive circuit, characterized in that the gate drive circuit of the MOSFET is turned off by an AND signal.