JPS58142624A - Phase controlling circuit - Google Patents
Phase controlling circuitInfo
- Publication number
- JPS58142624A JPS58142624A JP2413282A JP2413282A JPS58142624A JP S58142624 A JPS58142624 A JP S58142624A JP 2413282 A JP2413282 A JP 2413282A JP 2413282 A JP2413282 A JP 2413282A JP S58142624 A JPS58142624 A JP S58142624A
- Authority
- JP
- Japan
- Prior art keywords
- pulse transformer
- fet4
- pulse
- capacitor
- phase
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/13—Modifications for switching at zero crossing
Abstract
Description
【発明の詳細な説明】 本発明はゼロクロス・オン型の位相制御回路に関する。[Detailed description of the invention] The present invention relates to a zero-cross-on type phase control circuit.
位相制御方式による電力制御にはトライマツク、サイリ
スタなどのスイッチング素子が用いられ、制御される位
相に対応して導通させるが、第1図の基本動作波形にお
いて矢印Aで示されるようにスイッチング素子の導通時
に急峻な電圧、電流変化が生じ、大きなノイズを発生す
る。また、特に負荷がランプやモーターなどの場合、電
源投入時に大きなラッシュ電流が流れ、その対策を必要
とする。これをさくするため、第2図の出力電圧波形が
示すように、商用周波のゼロ位相(B点)でスイッチン
グ素子を導通させ、制御される位相に対R5、シて遮断
する(0点)と、ノイズ、ラッシュ電流共に小さくなり
、ノイズフィルタがfffiM([r+る。このような
ゼロクロス・オン型の0゛f相制御を行うには、スイッ
チング素子としてトランジスタ、ゲート・ターンオフサ
イリスタ4「どが用いられるが、トランジスタは、駆動
に制御回路を主回路と絶縁するパルストランスを使用し
たいm+ 合、商用周波の出力パルスが必要なためトラ
ンスの形状が大きくなり、価格が高くなり、GTOサイ
リスタは、ターンオフ時にかなり大きな電流の制御が必
要であり、駆動回路が複雑になるなど欠点が多い。Switching elements such as trimacs and thyristors are used for power control using the phase control method, and are made conductive in accordance with the controlled phase. Sometimes sudden changes in voltage or current occur, generating large noise. Furthermore, especially when the load is a lamp or motor, a large rush current flows when the power is turned on, and countermeasures are required. In order to reduce this, as shown in the output voltage waveform in Figure 2, the switching element is made conductive at the zero phase of the commercial frequency (point B), and the controlled phase is cut off by R5 (point 0). , both the noise and the rush current become small, and the noise filter becomes fffiM([r+. However, if you want to use a pulse transformer that isolates the control circuit from the main circuit for driving, the transformer size will be large and the price will be high because commercial frequency output pulses are required, and the GTO thyristor is There are many drawbacks, such as the need to control a fairly large current at turn-off and the drive circuit becoming complex.
本発明は上述の欠点を除去し、簡単な駆動回路で足りる
ゼロクロス・オン型位相制御回路を提供することを目的
とする。SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks and provide a zero-cross-on type phase control circuit that requires a simple drive circuit.
この目的は、位相制御回路のスイッチング素子として電
界効果トランジスタを用い、その電、界効来トランジス
タのゲート、ソース間にコンデンサを接続し、iのコン
デンサの両極に電源電圧の位相に対応して制御されるパ
ルストランスの出方電圧を印加することによって達成さ
れる。The purpose of this is to use a field effect transistor as the switching element of the phase control circuit, connect a capacitor between the gate and source of the field effect transistor, and control the voltage between both poles of the capacitor i in accordance with the phase of the power supply voltage. This is achieved by applying a voltage at the output of a pulse transformer.
以下図を引用して本発明の実施例について説明する。第
3図において、電源1に負荷2、整流ブIJ 7 シ3
オよび電界効果トランジスタ(FF:T)4カ接続さ
れている。F E ’I’ 4のゲート、ソース間には
、コンデンサ5とダイオード6を直列接続したパルスト
ランス7の二次巻線が並列に接続されている。Embodiments of the present invention will be described below with reference to the drawings. In Figure 3, power supply 1 has load 2, rectifier block IJ 7
and four field effect transistors (FF:T) are connected. A secondary winding of a pulse transformer 7 having a capacitor 5 and a diode 6 connected in series is connected in parallel between the gate and source of the F E 'I' 4.
パルストランス7の一次側には制御回路8が接続され、
この制御回路8は電源1の電圧のゼロ位相を検出し、パ
ルストランス7を介してFEiT4を駆動する。制御回
路8はパルストランスによって主回路と絶縁されている
。この場合FICTのゲート入力抵抗が大きいため、コ
ンデンサ5の両端電圧は、パルストランスの出力が間欠
パルス状であってもFETをオン状態に保つのに十分な
値に保持される。ダイオード6はこのコンデンサの電荷
がパルストランスの二次巻線を通じて放電するのを阻止
する。パルストランス7は、商用周波の周期に比べ極め
て幅の狭いパルスを伝送ずればよく、またパルス電流は
コンデンサ5の放電分のみを補えばよいので小形簡略化
が可能となる。パルストランス7の伝送パルスの周期は
コンデンサ5の放電時定数の数分の1程度に選べばよい
。第4図の各部動作波形が示すように、パルストランス
7は商用周波のゼロ位相に対応して制御回路8により制
御されパルス11を伝送し、FEiTをB点で導通させ
る。次に制御される位相に対応して制御回路8によりパ
ルス11の伝送が止められると、コンデンサ5の電荷は
ゲート抵抗を通して放電、シ、FKTは0点で遮断状態
となり第4図の出力波形12を示し、ゼロクロス・オン
型の位相制御が行われる。FETの遮断時間はゲート、
ソース間に抵抗を入れ、調整することも可能である。A control circuit 8 is connected to the primary side of the pulse transformer 7.
This control circuit 8 detects the zero phase of the voltage of the power supply 1 and drives the FEiT 4 via the pulse transformer 7. The control circuit 8 is insulated from the main circuit by a pulse transformer. In this case, since the gate input resistance of the FICT is large, the voltage across the capacitor 5 is maintained at a value sufficient to keep the FET in the on state even if the output of the pulse transformer is in an intermittent pulse form. Diode 6 prevents the charge on this capacitor from discharging through the secondary winding of the pulse transformer. The pulse transformer 7 only needs to transmit a pulse whose width is extremely narrow compared to the period of the commercial frequency, and the pulse current only needs to compensate for the discharge of the capacitor 5, so that it can be made smaller and simpler. The period of the transmission pulse of the pulse transformer 7 may be selected to be about a fraction of the discharge time constant of the capacitor 5. As shown in the operation waveforms of each part in FIG. 4, the pulse transformer 7 is controlled by the control circuit 8 in response to the zero phase of the commercial frequency, transmits the pulse 11, and makes the FEiT conductive at point B. When transmission of the pulse 11 is stopped by the control circuit 8 in response to the next controlled phase, the charge in the capacitor 5 is discharged through the gate resistor, and the FKT is cut off at the 0 point, resulting in the output waveform 12 in FIG. , and zero-cross-on type phase control is performed. The cutoff time of FET is gate,
It is also possible to adjust by inserting a resistor between the sources.
第3図に示す実施例で電力制御を行うためにはFIT
4にパワーFETを用いなければならないが、第3図と
共通の部分には同一の符号を付した第5図に示すように
バイポーラトランジスタ9を負荷2に直列に接続し、そ
のベースとコレクタ間にFET4を接続ずればFET4
の出力は小さくてすむ。In order to perform power control in the embodiment shown in FIG.
4, a bipolar transistor 9 is connected in series to the load 2, and a bipolar transistor 9 is connected in series between its base and collector as shown in FIG. 5, in which parts common to those in FIG. If you connect FET4 to
The output of is small.
以上述べたように本発明による位相制御回路はスイッチ
ング素子としてFITを用いたものであり、幅の狭いパ
ルスを伝送すればよい小形のパルストランスを用いるこ
とができ、簡単な駆動回路でFETを制御できるため、
近年法規制強化の動きのある低ノイズ化のためのゼロク
ロス−オン型位相制御回路として極めて有効に使用でき
る。As described above, the phase control circuit according to the present invention uses an FET as a switching element, and can use a small pulse transformer that only needs to transmit narrow pulses, and can control the FET with a simple drive circuit. Because you can
It can be used extremely effectively as a zero-cross-on type phase control circuit for noise reduction, which has recently been subject to stricter regulations.
第1図は位相制御回路動作波形の一例、第2図はゼロク
ロス・オン型位相制御回路動作波形の一例、第3図は本
発明の一実施例の回路図、第4図はそのパルストランス
およびFETの出力波形の一例、第5図は本発明の別の
実施例の回路図である。
1:電源、2=負荷、4:FKT、5:コンデンサ、6
:ダイオード、7:パルストランス、8:制御回路。
71図
才2図
2 才3図
〜 //467
1 /
) 二へ「、4′11
旦Fig. 1 is an example of the operating waveform of the phase control circuit, Fig. 2 is an example of the operating waveform of the zero-cross-on type phase control circuit, Fig. 3 is a circuit diagram of an embodiment of the present invention, and Fig. 4 is the pulse transformer and An example of the output waveform of the FET, FIG. 5 is a circuit diagram of another embodiment of the present invention. 1: Power supply, 2 = Load, 4: FKT, 5: Capacitor, 6
: Diode, 7: Pulse transformer, 8: Control circuit. 71 fig.
Claims (1)
スタを備え、該電界効果トランジスタのソース、ゲート
間にはコンデンサが接続され、該コンデンサの両極には
電源電圧の位相に対応して制御されるパルストランスの
出力電圧がダイオードを介して印加されることを特徴と
する位相制御回路。1) Equipped with a field effect transistor that can cut off the current flowing to the load, a capacitor is connected between the source and gate of the field effect transistor, and a pulse transformer that is controlled according to the phase of the power supply voltage is connected to both poles of the capacitor. A phase control circuit characterized in that an output voltage of is applied via a diode.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2413282A JPS58142624A (en) | 1982-02-17 | 1982-02-17 | Phase controlling circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2413282A JPS58142624A (en) | 1982-02-17 | 1982-02-17 | Phase controlling circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS58142624A true JPS58142624A (en) | 1983-08-24 |
Family
ID=12129779
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2413282A Pending JPS58142624A (en) | 1982-02-17 | 1982-02-17 | Phase controlling circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58142624A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04215945A (en) * | 1990-12-14 | 1992-08-06 | Toppan Printing Co Ltd | Biaxially oriented blow-molded bottle with handle |
-
1982
- 1982-02-17 JP JP2413282A patent/JPS58142624A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04215945A (en) * | 1990-12-14 | 1992-08-06 | Toppan Printing Co Ltd | Biaxially oriented blow-molded bottle with handle |
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