JPH06141542A - Switching power source circuit - Google Patents

Abstract

PURPOSE:To achieve high-speed switching and reduce loss due to continuity loss in a switching power source circuit of a stabilized power source. CONSTITUTION:Input terminal T11 is connected to one end of a primary terminal of a transformer TR, the other end of the primary terminal of the transformer TR is connected to the drain side of a field-effect transistor Q1, and source side of the field-effect transistor Q1 is connected to the input terminal T12. A capacitor C is connected to the input terminals T11 and T12 in parallel. An insulation gate bipolar mode transistor Q2 is connected to the other end of the primary terminal of the transformer TR and input terminal 12 in parallel with the field-effect transistor Q1. The collector terminal of the insulation gate bipolar mode transistor Q2 is connected to the other end of the primary terminal of the transformer TR and its emitter terminal is connected to the input terminal T12.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switching power supply circuit for a stabilized power supply device, and more particularly to a DC (Pulse)
(Width Modulation) The present invention relates to a switching power supply circuit that transforms and outputs according to a signal.

[0002]

2. Description of the Related Art A conventional switching power supply circuit includes one field effect transistor (FET) which receives a PWM signal output from a pulse width control circuit.
The DC voltage was intermittently output by r).

FIG. 4 is a diagram showing a conventional switching power supply circuit. In the figure, a switching power supply circuit 20
Is composed of a pulse width control circuit 21, a smoothing circuit 22, a capacitor C, a field effect transistor Q and a transformer TR. The pulse width control circuit 21 has an output terminal T
23, T24 output voltage is monitored, PW
The M signal Wp is output. The smoothing circuit 22 is a choke input type smoothing circuit including, for example, a diode, a coil and a capacitor. Since the specific circuit configurations of the pulse width control circuit 21 and the smoothing circuit 22 are known in the related art, the description thereof will be omitted.

As a power source for the input terminals T21 and T22,
A DC power source (not shown) is connected. This input terminal T21 is connected to one end of the primary side terminal of the transformer TR,
The other end of the primary side terminal of the transformer TR is connected to the drain side of the field effect transistor Q, and the source side of the field effect transistor Q is further connected to the input terminal T2.
It is connected to 2 and constitutes one closed circuit. In addition, PWM is provided on the gate side of the field effect transistor Q.
A pulse width control circuit 21 for outputting the signal Wp is connected.

The input terminal T is connected in parallel with the closed circuit.
A capacitor C is connected between 21 and the input terminal T22. The secondary terminal of the transformer TR is connected to the input side of the smoothing circuit 22, and the output side of the smoothing circuit 22 is connected to the output terminals T23 and T24.

With this circuit configuration, the input terminals T21,
The DC voltage input from T22 is the pulse width control circuit 2
The field effect transistor Q is switched by the PWM signal Wp output from 1. The DC voltage on the input side is converted by the transformer TR in accordance with the switching of the field effect transistor Q, and the DC voltage is output from the output terminals T23 and T24 via the smoothing circuit 22. Since this switching is performed at a relatively high speed, the PWM signal Wp
Therefore, the transition loss generated at the transition of rising and falling of the DC voltage is relatively small.

[0007]

However, since the field effect transistor Q has a high on-resistance between the drain-side terminal and the source-side terminal, there is a conduction loss in which the DC voltage drops by that amount. Therefore, when the current value is increased, the loss due to conduction loss cannot be ignored.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a switching power supply circuit that performs switching at high speed and reduces loss due to conduction loss.

[0009]

According to the present invention, in order to solve the above problems, a DC voltage is applied to a PWM (Pulse Width Modula).
a pulse width control circuit that outputs a PWM signal, a delay circuit that outputs a delay signal obtained by delaying the PWM signal by a predetermined time, PW
A logical product circuit that takes the logical product of the M signal and the delayed signal and outputs it as a switching signal, and a field effect transistor (FET; F; F that receives and interrupts the DC voltage in response to the delayed signal).
and an insulated gate bipolar mode transistor (IGBT) that is connected in parallel with the field effect transistor and that interrupts the DC voltage by receiving the switching signal.
and a switching power supply circuit.

[0010]

The delay circuit receiving the PWM signal output from the pulse width control circuit delays the signal by a predetermined time and outputs it as a delay signal. Further, the logical product circuit calculates the logical product of the PWM signal and the delay signal and outputs the logical product as a switching signal. The field effect transistor receives the delay signal to interrupt the DC voltage, and the insulated gate bipolar mode transistor connected in parallel with the field effect transistor receives the switching signal to interrupt the DC voltage.

With this configuration, when the PWM signal changes from OFF to ON, the field effect transistor (FE) is first
When T) turns on and the PWM signal makes a transition from on to off, the field effect transistor turns off after the gate voltage of the insulated gate bipolar mode transistor (IGBT) drops and the collector voltage drops first.

This insulated gate bipolar mode transistor has a low saturation voltage and a slow switching speed like a BJT (Bipolar Junction Transistor). For this reason,
By combining with the field effect transistor, the insulating bipolar mode transistor can be turned on while the field effect transistor is on, and conduction loss of the field effect transistor can be reduced. Further, by limiting the switching of the insulating bipolar mode transistor within the ON period of the field effect transistor, the switching loss of the insulating bipolar mode transistor can be reduced.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a switching power supply circuit of the present invention. In the figure, the switching power supply circuit 10 is
The pulse width control circuit 11, the delay circuit 12, the AND circuit 13, the smoothing circuit 14, the capacitor C, the field effect transistor (FET) Q1, the insulated gate bipolar mode transistor (IGBT) Q2, and the transformer TR. The pulse width control circuit 11 has an output terminal T1.
3, monitoring the output voltage output from T14, PWM
The signal Wp is output. The delay circuit 12 receives the PWM signal Wp and outputs a delayed signal Wd delayed by a predetermined time. The logical product circuit 13 receives the PWM signal Wp and the delay signal Wd and calculates the logical product, and outputs the calculation result as the switching signal Ws. In addition, the smoothing circuit 14
Is a choke input type smoothing circuit including, for example, a diode, a coil and a capacitor. The specific circuit configurations of the pulse width control circuit 11, the delay circuit 12, the logical product circuit 13, and the smoothing circuit 14 are known in the related art, and a description thereof will be omitted.

As a power source for the input terminals T11 and T12,
A DC power source (not shown) is connected. The input terminal T11 is connected to one end of the primary terminal of the transformer TR,
The other end of the primary side terminal of the transformer TR is connected to the drain side of the field effect transistor Q1, and the source side of the field effect transistor Q1 is connected to the input terminal T12 to form one closed circuit.

The input terminal T is connected in parallel with the closed circuit.
A capacitor C is connected between 11 and the input terminal T12. Further, the field effect transistor Q1 is provided between the other end of the primary side terminal of the transformer TR and the input terminal T12.
Insulated gate bipolar mode transistor Q in parallel with
2 is connected. The insulated gate bipolar mode transistor Q2 has a collector terminal connected to the other end of the primary side terminal of the transformer TR, and an emitter terminal connected to the input terminal T12.

The field effect transistor Q1 has a larger on-resistance than the insulated gate bipolar mode transistor Q2, and the time required for the transition between the conductive state and the cutoff state is sufficiently short. Hereinafter, for simplicity, only the switching time of the insulated gate bipolar mode transistor Q2 will be considered.

Next, the PWM signal Wp output from the pulse width control circuit 11 is applied to the delay circuit 12 and the AND circuit 1.
Input to 3. The delay circuit 12 receiving the PWM signal Wp outputs a delay signal Wd delayed by a predetermined time, specifically, a time indicated by the sum of a turn-off delay time and a falling time of the insulated gate bipolar mode transistor Q2 described later. . Since the output side of the delay circuit 12 is connected to the gate side of the field effect transistor Q1, the delay signal Wd is equal to the field effect transistor Q1.
Input to 1. Similarly, the AND circuit 13 which receives the PWM signal Wp and the delay signal Wd calculates the logical product of these signals and outputs it as the switching signal Ws. Since the output side of the AND circuit 13 is connected to the gate side of the insulated gate bipolar mode transistor Q2, the switching signal Ws is input to the insulated gate bipolar mode transistor Q2.

The secondary terminal of the transformer TR is connected to the input side of the smoothing circuit 14, and the output side of the smoothing circuit 14 is connected to the output terminals T13 and T14. With this circuit configuration, the DC voltage input from the input terminals T11 and T12 causes the delay signal W output from the delay circuit 12.
The field effect transistor Q1 is switched by d, and the switching signal W output from the AND circuit 13
Insulated gate bipolar mode transistor Q by s
2 is switched. At this time, when the PWM signal Wp changes from off to on, the field effect transistor Q1 is turned on first, and conversely, when the PWM signal Wp changes from on to off, the gate voltage of the insulated gate bipolar mode transistor Q2 is changed first. And the collector voltage decrease, the field effect transistor Q1 turns off.

Therefore, by connecting the insulated gate bipolar mode transistor Q2 having a low ON resistance in parallel with the field effect transistor Q1, conduction loss can be reduced.

Next, the turn-off delay time and fall time of the insulated gate bipolar mode transistor Q2 will be described. FIG. 2 is a diagram showing the turn-off delay time and the fall time. In this figure, the insulated gate bipolar mode transistor Q2 shown in FIG.
The case where s is received as the gate voltage V _GE to operate is shown.

According to the change of the switching signal Ws, the gate voltage V _GE changes from -5V to the positive side voltage of 1 at the time t1.
It reaches 0%, ie + 0.5V. Further, in response to the rise of the gate voltage V _GE , the current Ic flowing from the collector side to the emitter side of the insulated gate bipolar mode transistor Q2 at time t2 reaches 10% of this maximum current value, and at time t3, this maximum current value is reached. 90% of The time interval between time t1 and time t2 is the turn-on delay time t
d (on), and the time interval between time t2 and time t3 is the rising time tr. At this time, the collector voltage V _CE falls in response to the rise of the gate voltage V _GE .

At time t4, the gate voltage V _GE is + 5V.
Reaches 90% of the positive side voltage, that is, + 4.5V. Also, in response to the fall of the gate voltage V _GE ,
Insulated gate bipolar mode transistor Q at time t5
The current Ic flowing through 2 reaches 90% of this maximum current value,
At time t6, 10% of this maximum current value is reached. The time interval between time t4 and time t5 is the turn-off delay time td.
(off). At this time, the collector voltage V _CE rises in response to the fall of the gate voltage V _GE . The time interval between time t5 and time t6 is the fall time tf.

Next, the switching power supply circuit 10 of the present invention.
The operation of is explained using a time chart. Figure 3
3 is a time chart of the switching power supply circuit shown in FIG. This time chart shows the switching power supply circuit 1
0 shows a signal that changes with the passage of time, and the PWM signal Wp, the delay signal Wd, the switching signal Ws, and the current Ip flowing through the field effect transistor Q1 are shown from the top of the drawing.
And the signals of the current Ic flowing through the insulated gate bipolar mode transistor Q2.

When the PWM signal Wp rises at time t11, the turn-off delay time td shown in FIG. 2 starts at time t11.
(off) and the fall time tf, a time (hereinafter, simply referred to as “delay time td”) represented by the sum of the time t12.
At the same time, the delay signal Wd, the switching signal Ws and the current Ip rise. The current Ic completes its rising at time t13 due to the delay in switching of the insulated gate bipolar mode transistor Q2. Here, the drain-source voltage when the field effect transistor Q1 and the insulated gate bipolar mode transistor Q2 are conducting,
Both the collector-emitter voltage shall be sufficiently smaller than the input DC power supply voltage. Under this assumption, the current value when only the field effect transistor Q1 is conducting is determined by the ratio of the ON resistances of the field effect transistor Q1 and the insulated gate bipolar mode transistor Q2 after the insulated gate bipolar mode transistor Q2 becomes conductive. Is almost equal to the sum of the current values shunted to both sides.

Then, at the time t14, the switching signal Ws also falls with the fall of the PWM signal Wp. Also, the delay signal Wd falls at time t14 after a delay of time td from time t13. The current Ip once reaches the maximum current value at time t14 and then becomes ± 0 A according to the switching signal Wd. The current Ic starts to decrease after the turn-off delay time td (off) from the time t14 and becomes ± 0 A at the time t15.

Similarly, even if a pulse width different from the PWM signal Wp input at time t11 is input at time t21,
After a delay time td from the time t21, the delay signal Wd, the switching signal Ws and the current Ip rise at the time t22. The current Ic is delayed by the switching of the insulated gate bipolar mode transistor Q2 at time t23.
Completes the rise. Further, at the time t24, the switching signal Ws also falls with the fall of the PWM signal Wp, and the delay signal Wd completes the fall at the time t25 with a delay of the delay time td from the time t24. The current Ip once reaches the maximum current value at time t25 and then becomes ± 0 A according to the switching signal Wd. The current Ic starts decreasing after the turn-off delay time td (off) from the time t24 and becomes ± 0 A at the time t25.

Thus, when the PWM signal Wp transitions from OFF to ON, the field effect transistor Q1 receiving the delay signal Wd is turned ON first (time t12, t22), and then the insulated gate bipolar mode transistor Q2 is turned ON ( Time t13, t23). On the contrary, when the PWM signal Wp transitions from ON to OFF, the insulated gate bipolar mode transistor Q2 receiving the switching signal Ws starts to turn off first (time t14, t24), and then turns off together with the field effect transistor Q1 ( Time t1
5, t25), the transition loss due to the ON / OFF of the PWM signal Wp can be reduced.

Further, the insulated gate bipolar mode transistor Q2 having a low ON resistance is replaced by the field effect transistor Q.
By connecting in parallel with 1, reduce conduction loss,
It is possible to prevent the output voltage from decreasing.

Furthermore, by setting the delay time td to the time represented by the sum of the turn-off delay time td (off) and the fall time tf, the insulated gate bipolar mode transistor Q2 is turned on while the field effect transistor Q1 is on. The off operation can be reliably performed.

In the above description, the field effect transistor Q
Although the switching time of 1 is "0" and the delay time td is the time shown by the sum of the turn-off delay time td (off) and the falling time tf, the field effect transistor Q1 and the insulated gate used are not limited to this. Depending on the combination of the bipolar mode transistors Q2, the optimum time may be set so that the insulated gate bipolar mode transistor Q2 can be surely turned off while the field effect transistor Q1 is on.

[0031]

As described above, in the present invention, the delay circuit receiving the PWM signal output from the pulse width control circuit outputs the delay signal, the AND circuit outputs the switching signal, and the field effect transistor The insulated gate bipolar mode transistor connected in parallel to the field effect transistor receives the delay signal to interrupt the DC voltage, and receives the switching signal to interrupt the DC voltage. The loss can be reduced, and the conduction loss can be reduced by the insulated gate bipolar mode transistor.

Therefore, the heat loss of the entire switching power supply circuit can be reduced by reducing the transition loss and the conduction loss, so that the volume of the radiator can be reduced.

[Brief description of drawings]

FIG. 1 is a diagram showing a switching power supply circuit of the present invention.

FIG. 2 is a diagram showing an accumulation time and a fall time.

FIG. 3 is a time chart of the switching power supply circuit shown in FIG.

FIG. 4 is a diagram showing a conventional switching power supply circuit.

[Explanation of symbols]

10 switching power supply circuit 11 pulse width control circuit 12 delay circuit 13 AND circuit 14 smoothing circuit Q1 FET (Field Effect Transistor) Q2 IGBT (Insulated Gate Bipolar mode Transi)
stor; insulated gate bipolar mode transistor) TR transformer C smoothing capacitor Wp PWM (Pulse Width Modulation) signal Wd delay signal Ws switching signal

Claims (2)

[Claims] 1. A DC (Pulse Width Modula)
a pulse width control circuit for outputting a PWM signal, the pulse width control circuit outputting a PWM signal, a delay circuit outputting a delay signal obtained by delaying the PWM signal by a predetermined time, A logical product circuit that obtains a logical product of a PWM signal and the delay signal and outputs it as a switching signal, a field effect transistor (FET) that receives the delay signal and interrupts a DC voltage, and the field effect transistor And an insulated gate bipolar mode transistor (IGBT; Insulate) connected in parallel with the switching signal to interrupt the DC voltage.
d Gate Bipolar mode Transistor) and a switching power supply circuit. 2. The switching power supply circuit according to claim 1, wherein the delay circuit is configured such that the predetermined time is a sum of a turn-off delay time and a fall time of the insulated gate bipolar mode transistor. .