JPS6180833A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6180833A JPS6180833A JP20152084A JP20152084A JPS6180833A JP S6180833 A JPS6180833 A JP S6180833A JP 20152084 A JP20152084 A JP 20152084A JP 20152084 A JP20152084 A JP 20152084A JP S6180833 A JPS6180833 A JP S6180833A
- Authority
- JP
- Japan
- Prior art keywords
- film
- substrate
- etching
- insulating film
- recess
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の属する技術分野〕
本発明は、半導体装置とその製造方法に関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention relates to a semiconductor device and a method for manufacturing the same.
従来、絶縁V埋め込み型の素子分離法において素子分離
工程が終了した後の槙々のフッ酸系の処理において分離
領域の絶縁膜がエツチングされ第3図〜)に示すように
素子領域の角が露出してしまう。このよう(こ素子領域
中の角が一出すると角の部分での電界集中が強くなり、
リーク電流が増大するこのリーク電流がトランジスタの
特性を劣化させ、さらに歩留りが低下して来る。Conventionally, in the insulating V-embedded device isolation method, the insulating film in the isolation region is etched in a hydrofluoric acid treatment after the device isolation process is completed, and the corners of the device region are It will be exposed. In this way (when a corner in the element region is exposed, the electric field concentration at the corner becomes stronger,
This leakage current, which increases the leakage current, deteriorates the characteristics of the transistor and further reduces the yield.
L発明の目的〕
本発明の目的は素子外1に形成後のフッ酸系の処理によ
る素子分離領域(フィールド領域)の絶縁−の後退によ
る角のJ出を防ぐことによりトランジスタ特性の向上を
図ろための半導体装置とその製造方法を提供することに
ある。LObject of the Invention] The object of the present invention is to improve transistor characteristics by preventing corner protrusion due to regression of insulation in the element isolation region (field region) due to hydrofluoric acid treatment after formation outside the element. An object of the present invention is to provide a semiconductor device for filtering and a method for manufacturing the same.
本発明は絶瞳膜をSi基板凹部に少なくとも凹部以外の
Si表面よりも盛り上がらせて埋め込む事により前記角
の露出をおさえ、トランジスタの劣化を防ぐものである
。The present invention suppresses the exposure of the corners by embedding the pupil-stopping film in the recessed portions of the Si substrate so that it is raised higher than at least the Si surface other than the recessed portions, thereby preventing deterioration of the transistor.
本発明により8i基板凹部に埋め込まれる絶縁膜は凹部
以外のSi表面よりも盛り上げられて形成される(第1
図)。これにより、例えば酸化前処理等のフッ酸系の処
理でのSi基板凹部の角が露出する事はない。そのため
トランジスタ特性の劣化が著しくおさえられ、果槽回路
の信頼性も向上し、歩留まりも飛躍的に向上した。According to the present invention, the insulating film embedded in the 8i substrate recess is formed to be raised higher than the Si surface other than the recess (first
figure). This prevents the corners of the recessed portions of the Si substrate from being exposed during hydrofluoric acid treatment such as oxidation pretreatment. As a result, the deterioration of transistor characteristics was significantly suppressed, the reliability of the cell circuit was improved, and yields were dramatically improved.
本発明の一災施例を第2図ら)〜th)を用いて説明す
る。A disaster example of the present invention will be explained using FIGS.
まず初めにS」基板(1)例えばp iJlの面方位(
100)の基板を用意し、熱酸化膜(2)を例えば10
0(l程度形成する。次に例えばリンドープのpoly
−8i(3)を4000A程度デボした後さらに例えば
S 、i 0゜lf!<41を4000A程度形成する
。次に通常の写真蝕智
刻工程によりバターニングを行い、第2図((支)のよ
うな構造を得る。次にレジスト6)をマスクにSin。First of all, the surface orientation of the S'' substrate (1), for example, p iJl (
Prepare a substrate of 100) and apply a thermal oxide film (2) of, for example, 10
0 (about 1 is formed. Next, for example, phosphorus-doped poly
After debossing -8i (3) by about 4000A, for example, S, i 0゜lf! <41 is formed to approximately 4000A. Next, patterning is performed using a normal photoetching process to obtain a structure as shown in FIG.
(4)とpoly−8if31を例えば反応性イオンエ
ツチングで異方的にエツチングする渠2メib)。天に
310゜膜イ2) 、 +41 ヲマス/ 4コp o
I y −8i (31ヲ尋方的lCエツチングし、
diO,[J(4)のパターンより内聞にpoly”−
8it31を侵退させる。その暁レジスト151ヲマス
クに” ’ 0* 膜12)を列えば[Igでエツチン
グする。(4) and poly-8if31 are etched anisotropically, for example, by reactive ion etching. 310° film in the sky 2), +41 womas / 4 cops o
I y -8i (31-dimensional IC etching,
diO, [poly”-
Invade 8it31. If a ``0* film 12) is arranged on the mask of the dawn resist 151, it is etched with Ig.
ズにレジスト(5)を1虞去した鎌、S i O!唆(
41をマスクにSi4仮を列えばRIBを用いてエツチ
ングし例えば深さ約0.7μmの4を形成する。犬に8
i011虞(4)を除去した鎌、例えばポロンとリンを
含んだ絶縁膜[3P S G+6)を1.0μm程変デ
ボし、熱処理例えば950℃、30分N、中で行えばS
i苓仮(1)に不純物が拡散する。欠に前記BPSG1
61を除去した後絶縁膜であろCVD−8in、@)を
例えば1.2μm桿L(デポする。次に流動性被膜(9
)例えばレジストで平坦化を行いレジタhとCVD−8
i0.(Siを反応1+:イオンエツチングを用いて少
なくともレジストのエツチングレートよりSiO,のエ
ツチングレートが速い条件でエッチバックを行なう。粁
点はpo l y−8i (3)の表面が出て来た所と
する。ここまでの構造・e第2図C−に示す。次に、p
oly−8i f31を除去すれば$2図(んのような
si基板凹に絶縁1漢(8)が盛り上がって形成される
。さらに凹部の横方向にもi’j3 @ 129 ”が
形成されているので本発明の分離構造が得られる。本実
施しリで(ば等方的にエツチングされる膜(3)として
ポリシリコンを用いたが、これはシリコン鼠化喚でもよ
く。SiO!, the sickle that removed one resist (5) from Z! Suggestion (
Using 41 as a mask, a temporary Si4 layer is placed and etched using RIB to form 4 with a depth of about 0.7 μm, for example. 8 for dogs
If an insulating film containing poron and phosphorus [3P S G+6] is deformed by about 1.0 μm using a sickle from which the i011 risk (4) has been removed, and heat treatment is performed at 950°C for 30 minutes in N, S
Impurities diffuse into i Reika (1). Absolutely the above BPSG1
After removing 61, deposit an insulating film (CVD-8in, @) with a thickness of 1.2 μm, for example.
) For example, planarize with resist and create resistor h and CVD-8.
i0. (Reaction 1+ for Si: Etch back using ion etching under conditions where the etching rate of SiO is faster than the etching rate of the resist. The point is where the surface of poly y-8i (3) appears. The structure so far e is shown in Figure 2 C-.Next, p
If oly-8i f31 is removed, an insulating layer (8) will be formed in the Si substrate concavity as shown in Figure 2.Furthermore, i'j3@129'' will be formed in the lateral direction of the concave portion. In this embodiment, for example, polysilicon was used as the film (3) to be etched isotropically, but it may also be silicon oxide.
さらにボロンの拡散1〜(7)をB P 8 G161
をデボした後の熱処理工程で形成したがイオン注入法で
も同様の効果が得られる。Furthermore, boron diffusion 1 to (7) is B P 8 G161
Although it is formed by a heat treatment process after debossing, the same effect can be obtained by ion implantation.
又、凹部の深さをd、フィールド酸化膜の、1輸り上が
りを31周辺部への広がりをb1フィールドIn addition, the depth of the recess is d, and the rise of the field oxide film is 31, and the spread to the periphery is b1 field.
第1図及び萬2図(at〜−)は本発明を説明するため
の断面図、惧3図(at (blは従来例を説明するた
めの断面図である。Figures 1 and 2 (at to -) are cross-sectional views for explaining the present invention, and Figures 3 and 3 are cross-sectional views for explaining a conventional example.
Claims (4)
形成し、凹部にフィールド酸化膜がシリコン基板表面よ
りaだけ盛り上がり、周辺部でbだけ広がって存在し、
上記a、bはフィールド酸化膜のフィールド酸化膜形成
後の膜減り量をcとした時c<a<d/2、c<b<d
/2でそれぞれ表わされる事を特徴とする半導体装置の
製造方法。(1) A recess with a depth d is formed in the element isolation region on the surface of the semiconductor substrate, and a field oxide film is present in the recess, protruding by an amount a from the silicon substrate surface and expanding by an amount b at the periphery,
The above a and b are c<a<d/2, c<b<d, where c is the amount of film reduction after the field oxide film is formed.
A method for manufacturing a semiconductor device, characterized in that each is represented by /2.
真蝕刻技術により前記周辺で延在する絶縁膜を形成する
工程を備えた事を特徴とする前記特許請求の範囲第1項
記載の半導体装置の製造方法。(2) The semiconductor according to claim 1, further comprising the step of forming an insulating film extending around the periphery by a normal photolithography technique when embedding the insulating film in the recess. Method of manufacturing the device.
を積層する工程と、さらに第3の膜を形成する工程と、
前記第3の膜を写真蝕刻工程によりエッチングする工程
と、さらに第3の膜をマスクに前記第2のマスクをエッ
チングする工程と、前記第3の膜と同じ形状に第2の膜
をエッチングする工程と前記第1の絶縁膜を第3の膜を
マスクにエッチングする工程と、少なくとも前記第1の
膜をマスクにSi基板をエッチングし凹部を形成する工
程と、第3の膜を形成する工程と、前記第3の膜上に流
動性被膜を形成しエッチングする事により前記Si基板
に凹部を形成する工程と、前記第3の膜を除去した後全
面に第4の絶縁性被膜を堆積する工程と、前記第4の絶
縁性被膜を少なくとも一部エッチングする事により少な
くとも前記Si凹部に埋め込む工程とを備えた事を特徴
とする前記特許請求の範囲第1項記載の半導体装置の製
造方法。(3) a step of forming a first film on a semiconductor substrate, a step of stacking a second film, and a step of further forming a third film;
etching the third film by photolithography; further etching the second mask using the third film as a mask; and etching the second film in the same shape as the third film. a step of etching the first insulating film using a third film as a mask; a step of etching the Si substrate using at least the first film as a mask to form a recess; and a step of forming a third film. forming a recess in the Si substrate by forming and etching a fluid film on the third film; and depositing a fourth insulating film on the entire surface after removing the third film. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising the steps of: etching at least a portion of the fourth insulating film to bury at least the Si recess.
記第2の膜はシリコン窒化膜、またはpoly−Si膜
である事を特徴とする前記特許請求の範囲第3項記載の
半導体装置の製造方法。(4) The semiconductor according to claim 3, wherein the first and third films are silicon oxide films, and the second film is a silicon nitride film or a poly-Si film. Method of manufacturing the device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP20152084A JPS6180833A (en) | 1984-09-28 | 1984-09-28 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP20152084A JPS6180833A (en) | 1984-09-28 | 1984-09-28 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6180833A true JPS6180833A (en) | 1986-04-24 |
Family
ID=16442405
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP20152084A Pending JPS6180833A (en) | 1984-09-28 | 1984-09-28 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6180833A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5433794A (en) * | 1992-12-10 | 1995-07-18 | Micron Technology, Inc. | Spacers used to form isolation trenches with improved corners |
-
1984
- 1984-09-28 JP JP20152084A patent/JPS6180833A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5433794A (en) * | 1992-12-10 | 1995-07-18 | Micron Technology, Inc. | Spacers used to form isolation trenches with improved corners |
US5733383A (en) * | 1992-12-10 | 1998-03-31 | Micron Technology, Inc. | Spacers used to form isolation trenches with improved corners |
US5868870A (en) * | 1992-12-10 | 1999-02-09 | Micron Technology, Inc. | Isolation structure of a shallow semiconductor device trench |
US5966615A (en) * | 1992-12-10 | 1999-10-12 | Micron Technology, Inc. | Method of trench isolation using spacers to form isolation trenches with protected corners |
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