JPS6179397A - Scanning system - Google Patents

Abstract

PURPOSE:To quicken the reading speed by driving a common TR switch always once in reading switch information belonging to one line of matrix form. CONSTITUTION:In reading the switch information of switches S11, S12, S13,...S1m belonging to the 1st line, a signal is fed to the base of a transistor (TR)1 to turn on it and read amplifiers SA1, SA2, SA3,-,SAm are operated in such a state. The output of the amplifiers SA1-SA8 is read via a selector SEL. The output of the SA9-SA12 sets respectively only flip-flops F9-F12, then the selector SEL is activated at the next step, the information of the flip- flops F9-F12 is read and inputted to a microprocessor. Since the information of the flip-flops F9-F12 in the 2nd step is read in high speed, the time required for reading the switch information of the switches S11, S12, S13...S1m belonging to the 1st line is reduced remarkably in comparison with a conventional system even if (m) is larger than 8.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a circuit system for scanning and reading key information in digital equipment such as electronic exchanges.

[Conventional technology]

2. Description of the Related Art Digital equipment such as electronic exchanges requires a circuit that reads information from a large number of keys used on operation panels and the like.

Normally, a key is configured in a matrix format with m columns and n rows (m and n are both integers), and when reading this key, a method is used to read it all at once in one row.

FIG. 2 shows an example of a circuit for reading conventional matrix-type key information.

In the figure, Tr] to Trn are transistor switches that control the switches belonging to the first to nth rows, respectively;
ol, S12, S13...S1m is the switch belonging to the first row, Snl, Sn2.8 port 3...Snm is the switch belonging to the 0th row
Switches belonging to the row, SAI, SA2, SA3
. . . SAm is a read amplifier for the first column to the second column, SEL is a selector, and MPU is a microprocessor. The same symbols represent the same objects throughout all the figures below.

Switches Sll, S12, and S belonging to the first row in FIG.
13...When reading the switch status of S1m, apply a signal to the base of transistor 1r1 to turn it on, and in this state read amplifiers S A1, SA2,
SA3... Operate SAm and read.

Similarly, the switches Snl, Sn2, belonging to the nth row
When reading the switch information of Sn3...Snm, apply a signal to the terminals of the transistors Trn to turn them on, and in this state, read out the amplifiers SAI, SAI and SNM as before.
SA2, SA3... Operate SAm and read. That is, it is a format in which m takes can be read simultaneously.

However, when trying to implement this circuit using an 8-tip microprocessor, when m is 83L or a larger number, for example 12, a 1-run transistor Tr is usually used.
Drive n twice and read.

That is, taking as an example the case where the switch information ti of the younger brother n row is read, the outputs of the reading amplifiers 5A1-3A8 are sent to the microprocessor M by the selector SEL.
It is connected to the input of PU, applies a signal to the base of transistor Trn to turn it on, and reads the information of switches Snl to Sn8 among the switch information in the first row.

Next, switch the selector S E L and select SA9 to 5A12.
After connecting the output of the microprocessor MPU to the input of the microprocessor MPU, the input signal of the transistor Trn is applied again to turn it on, and among the switch information in the nth row, the switch Sn9
~5n12 information was being read.

[Problem that the invention seeks to solve]

The above method is used to read key information in matrix format, but matrix format keys have long wiring due to their structure and therefore have a large amount of stray capacitance, so it is difficult to read them at high speed. There is a problem that in a device that requires high-speed operation, it is inappropriate to drive the transistor Trn twice in order to read switch information in the same row because it reduces the speed.

[Means for solving problems]

A means for solving the problem is that when key information configured in a matrix format having a plurality of m columns of key elements in one row is read using a microprocessor having a plurality of n bits smaller than the plurality of rn, the key elements of the column are By operating a transistor switch that drives both m and m belonging to the column,
Among the key information, n pieces of information are read by the microprocessor via a selector, and the remaining key information is written to (rn-n) flip-flops, and in the next step, the selector Switch the (m-
This is achieved by a scanning method in which the microprocessor reads rare key information written to n) flip-flops.

[Effect]

That is, according to the present invention, when reading the switch information belonging to one row of the matrix format, the common transistor switch is always driven once, and the reading time of the flip-flop is very short, so the readability is faster than in the conventional method. This has the effect of increasing the picking speed.

〔Example〕

FIG. 1 is a block diagram showing one embodiment of a scanning method according to the present invention.

In the figure, F9 to F12 are flip-flops, respectively.

The present invention will be described in detail below with reference to the drawings.

For example, the switches Sll, Sl, 2, S belonging to the first row
13...When reading the switch information of S1m, apply a signal to the base of transistor Tr 1 to turn it on,
In this state, the readout amplifiers SAI, SA2, SA3
... Operate SAm.

At this time, the outputs of readout amplifiers SAI to SA8 are read out via selector SEL, and the outputs of SA9 to SA12 only set flip-flops F9 to F12, respectively, but in the next step selector SE L is operated to read the information of flip-flops F9 to F12 and input it to the microprocessor.

This division is the same as the conventional method, but since the information of the flip-flops F9 to F12 in the second step can be read at high speed, the switches Sll and S12 belonging to the first row , Si2...Sum can be significantly reduced compared to the conventional method even when m is a value larger than 8 (but not greater than 16).

〔Effect of the invention〕

As described in detail above, the present invention has the great effect of being able to realize a scanning system that operates at extremely high speeds.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of a scanning method according to the present invention. FIG. 2 shows an example of a circuit for reading conventional matrix-type key information. In the figure, Tr ] ~ Tr n i, 1, respectively, 1st row to nth row
l transistors that control the switches belonging to each row, S11, S12, S13...S1m are the switches belonging to the first row, Snl, Sn2, SSn3-3
If n is the switch belonging to the 0th row, SAI, SA2, S
A3...SAm are readout amplifiers for the first to mth columns, respectively, F9 to F12 are flip-flops, and S
T'? , L is a selector, and MPU is a microprocessor.

Claims (1)

[Claims] When key information configured in a matrix format having a plurality of m columns of key elements in one row is read using a microprocessor having a plurality of n bits less than m, a transistor switch that commonly drives the columns is operated. hand,
Read n pieces of key information out of m pieces of key information belonging to the column by the microprocessor via a selector, write the remaining key information to (m-n) flip-flops, and proceed to the next step. A scanning method characterized in that the microprocessor reads key information written in the (m−n) flip-flops by switching the selector at the (m−n) flip-flops.