JPS6179397A - Scanning system - Google Patents

Scanning system

Info

Publication number
JPS6179397A
JPS6179397A JP20123984A JP20123984A JPS6179397A JP S6179397 A JPS6179397 A JP S6179397A JP 20123984 A JP20123984 A JP 20123984A JP 20123984 A JP20123984 A JP 20123984A JP S6179397 A JPS6179397 A JP S6179397A
Authority
JP
Japan
Prior art keywords
read
flip
flops
information
belonging
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20123984A
Other languages
Japanese (ja)
Inventor
Shinichi Maeno
前野 真一
Tsutomu Sato
勉 佐藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Nippon Telegraph and Telephone Corp
Original Assignee
Fujitsu Ltd
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Nippon Telegraph and Telephone Corp filed Critical Fujitsu Ltd
Priority to JP20123984A priority Critical patent/JPS6179397A/en
Publication of JPS6179397A publication Critical patent/JPS6179397A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04QSELECTING
    • H04Q3/00Selecting arrangements
    • H04Q3/72Finding out and indicating number of calling subscriber

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Interface Circuits In Exchanges (AREA)

Abstract

PURPOSE:To quicken the reading speed by driving a common TR switch always once in reading switch information belonging to one line of matrix form. CONSTITUTION:In reading the switch information of switches S11, S12, S13,...S1m belonging to the 1st line, a signal is fed to the base of a transistor (TR)1 to turn on it and read amplifiers SA1, SA2, SA3,-,SAm are operated in such a state. The output of the amplifiers SA1-SA8 is read via a selector SEL. The output of the SA9-SA12 sets respectively only flip-flops F9-F12, then the selector SEL is activated at the next step, the information of the flip- flops F9-F12 is read and inputted to a microprocessor. Since the information of the flip-flops F9-F12 in the 2nd step is read in high speed, the time required for reading the switch information of the switches S11, S12, S13...S1m belonging to the 1st line is reduced remarkably in comparison with a conventional system even if (m) is larger than 8.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は電子交換機等のディジタル機器に於いて、キー
情報を走査して読み取る回路方式に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a circuit system for scanning and reading key information in digital equipment such as electronic exchanges.

〔従来の技術〕[Conventional technology]

電子交換機等のディジタル機器に於いて、操作盤等に使
用されている多数のキー情報を読み取る回路が必要であ
る。
2. Description of the Related Art Digital equipment such as electronic exchanges requires a circuit that reads information from a large number of keys used on operation panels and the like.

普通キーはm列、n行のマトリックス形式(m、nは共
に整数)で構成され、此れを読み取る時は1行事位に一
括読み取る方法をとっている。
Normally, a key is configured in a matrix format with m columns and n rows (m and n are both integers), and when reading this key, a method is used to read it all at once in one row.

第2図は従来のマトリックス形式のキー情報を読み取る
回路の一例を示す。
FIG. 2 shows an example of a circuit for reading conventional matrix-type key information.

図中、Tr ]〜Trnは夫々第1行〜第n行の各行に
所属するスイッチを制御するトランジスタスイッチ、S
ol、S12、S13・・・S1mは第1行に所属する
スイッチ、Snl、Sn2.8口3・・・Snmは第0
行に所属するスイッチ、SAI 、SA2、SA3  
・・・SAmは夫々第1列〜第用列の読め出し用増幅器
、SELはセレクタ、MPUはマイクロプロセッサであ
る。尚以下全図を通じ同一記号は同一対象物を表す。
In the figure, Tr] to Trn are transistor switches that control the switches belonging to the first to nth rows, respectively;
ol, S12, S13...S1m is the switch belonging to the first row, Snl, Sn2.8 port 3...Snm is the switch belonging to the 0th row
Switches belonging to the row, SAI, SA2, SA3
. . . SAm is a read amplifier for the first column to the second column, SEL is a selector, and MPU is a microprocessor. The same symbols represent the same objects throughout all the figures below.

第2図の第1行に所属するスイッチSll、S12、S
13・・・S1mのスイッチ情幸■を読み取る時は、ト
ランジスタ1゛r 1のヘースに信号を印加してオンと
し、此の状態で読め出し用増幅器S A 1、SA2、
SA3  ・・・SAmを動作させて読め取る。
Switches Sll, S12, and S belonging to the first row in FIG.
13...When reading the switch status of S1m, apply a signal to the base of transistor 1r1 to turn it on, and in this state read amplifiers S A1, SA2,
SA3... Operate SAm and read.

同様Oこ第n行に所属するスイッチSnl、 Sn2、
Sn3・・・Snmのスイッチ情報を読め取る時は、ト
ランジスタTr nの−・−スに信号を印加してオンと
し、此の状態で前と同じく読み出し用増幅器SAI 、
SA2 、SA3  ・・・SAmを動作させて読め取
る。即ちm個のテークを同時並行して読め取る形式であ
る。
Similarly, the switches Snl, Sn2, belonging to the nth row
When reading the switch information of Sn3...Snm, apply a signal to the terminals of the transistors Trn to turn them on, and in this state, read out the amplifiers SAI, SAI and SNM as before.
SA2, SA3... Operate SAm and read. That is, it is a format in which m takes can be read simultaneously.

然し、8ヒントのマイクロプロセッサを使用して此の回
路を実現しようとする場合、前記のmが83L、り大き
い数字、例えば12である時には普通1ランシスタTr
nを2回駆動して読め取る。
However, when trying to implement this circuit using an 8-tip microprocessor, when m is 83L or a larger number, for example 12, a 1-run transistor Tr is usually used.
Drive n twice and read.

即ち、令弟n行のスイッチ情tiを読め取る場合を例に
取って説明すると、読め出し用増幅器5A1−3A8の
出力をセレクタS E LによりマイクロプロセッサM
 P Uの入力に接続し、トランジスタTrnのヘース
に信号を印加してオンとし、第1行のスイッチ情報の内
、スイッチSnl〜Sn8の情報を読み取る。
That is, taking as an example the case where the switch information ti of the younger brother n row is read, the outputs of the reading amplifiers 5A1-3A8 are sent to the microprocessor M by the selector SEL.
It is connected to the input of PU, applies a signal to the base of transistor Trn to turn it on, and reads the information of switches Snl to Sn8 among the switch information in the first row.

次にセレクタS E Lを切り換えてSA9〜5A12
の出力をマイクロプロセッサMPUの入力に接続してか
ら再びトランジスタTr nのヘースニ信号を印加して
オンとし、第n行のスイッチ情報の内、スイッチSn9
〜5n12の情報を読み取っていた。
Next, switch the selector S E L and select SA9 to 5A12.
After connecting the output of the microprocessor MPU to the input of the microprocessor MPU, the input signal of the transistor Trn is applied again to turn it on, and among the switch information in the nth row, the switch Sn9
~5n12 information was being read.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

マトリックス形式のキー情報を読み取る場合には上記の
方法に依って行われているが、−iにマトリックス形式
のキーは構造上配線が長くなり、従って浮遊容量が多く
なるため高速度で読み取るには限界があり、高速動作を
要求される装置に於いて同一の行のスイッチ情報を読み
取るためトランジスタTr nを2回駆動することは速
度を低下させるので不適当であると云う問題がある。
The above method is used to read key information in matrix format, but matrix format keys have long wiring due to their structure and therefore have a large amount of stray capacitance, so it is difficult to read them at high speed. There is a problem that in a device that requires high-speed operation, it is inappropriate to drive the transistor Trn twice in order to read switch information in the same row because it reduces the speed.

〔問題点を解決するための手段〕[Means for solving problems]

問題点を解決するための手段は、1行に複数m列のキー
素子を有するマトリックス形式で構成されたキー情報を
複数rnより少ない複数nビット構成のマイクロプロセ
ッサを使用して読み取る場合、該列を共imに駆動する
トランジスタスイッチを動作させて、該列に所属するm
個の該キー情報の内n個の該−トー情報をセレクタ経由
マイクロプロセッサにより読み取り、月、つ残余の該キ
ー情報を(rn−n )個のフリップ・フロップに書き
込め、次のステップで該セレクタを切り替えて該(m−
n)個のフリップ・フロップに書き込むまれだキー情報
を該マイクロプロセッサにより読み取る走査方式により
達成される。
A means for solving the problem is that when key information configured in a matrix format having a plurality of m columns of key elements in one row is read using a microprocessor having a plurality of n bits smaller than the plurality of rn, the key elements of the column are By operating a transistor switch that drives both m and m belonging to the column,
Among the key information, n pieces of information are read by the microprocessor via a selector, and the remaining key information is written to (rn-n) flip-flops, and in the next step, the selector Switch the (m-
This is achieved by a scanning method in which the microprocessor reads rare key information written to n) flip-flops.

〔作用〕[Effect]

即ち、本発明に依るとマトリックス形式の1行に所属す
るスイッチ情報を読み取る時、共通トランジスタスイッ
チの駆動回数が常に1回となり、フリップ・フロップの
読み取り時間は僅少であるので従来方式に比し読め取り
速度を早く出来ると云う効果が生まれる。
That is, according to the present invention, when reading the switch information belonging to one row of the matrix format, the common transistor switch is always driven once, and the reading time of the flip-flop is very short, so the readability is faster than in the conventional method. This has the effect of increasing the picking speed.

〔実施例〕〔Example〕

第1図は本発明に依る走査方式の一実施例を示すブロッ
ク図である。
FIG. 1 is a block diagram showing one embodiment of a scanning method according to the present invention.

図中、F9〜F12は夫々フリップ・フロップである。In the figure, F9 to F12 are flip-flops, respectively.

以下図に従って本発明の詳細な説明する。The present invention will be described in detail below with reference to the drawings.

例えば第1行に所属するスイッチSll、Sl、2、S
13・・・S1mのスイッチ情報を読め取る時は、トラ
ンジスタTr 1のヘースに信号を印加してオンとし、
此の状態で読み出し用増幅器SAI、SA2 、SA3
  ・・・SAmを動作させる。
For example, the switches Sll, Sl, 2, S belonging to the first row
13...When reading the switch information of S1m, apply a signal to the base of transistor Tr 1 to turn it on,
In this state, the readout amplifiers SAI, SA2, SA3
... Operate SAm.

此の時読み出し用増幅器SAI〜SA8の出力はセレク
タSELを経由して読み出され、SA9〜5A12の出
力は夫々フリップ・フロップF9〜F12をセットする
のみであるが、次のステップでセレクタS E Lを動
作させてフリップ・フロップF9〜F12の情報を読み
取り、マイクロプロセッサに入力する。
At this time, the outputs of readout amplifiers SAI to SA8 are read out via selector SEL, and the outputs of SA9 to SA12 only set flip-flops F9 to F12, respectively, but in the next step selector SE L is operated to read the information of flip-flops F9 to F12 and input it to the microprocessor.

此の様に2回に分ける点は従来方式と同一であるが、第
2ステツプのフリップ・フロップF9〜F12の情報を
読み取るのは高速で実施出来るので、第1行に所属する
スイッチSll、S12、Si2・・・Sumのスイッ
チ情報を読み取るに必要な時間は、mか8より大きい値
(但し16以下とする)であっても従来方式に比し大幅
に減少出来る。
This division is the same as the conventional method, but since the information of the flip-flops F9 to F12 in the second step can be read at high speed, the switches Sll and S12 belonging to the first row , Si2...Sum can be significantly reduced compared to the conventional method even when m is a value larger than 8 (but not greater than 16).

〔発明の効果〕〔Effect of the invention〕

以−ト詳細に説明した様に本発明によれば、極めて高速
度で動作する走査方式を実現出来ると云・う大きい効果
がある。
As described in detail above, the present invention has the great effect of being able to realize a scanning system that operates at extremely high speeds.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明に依る走査方式の一実施例を示すブロッ
ク図である。 第2図は従来のマトリックス形式のキー情報を読み取る
回路の一例を示す。 図中、Tr ] 〜Tr n i、1夫々第1行〜第n
行の各行に所属するスイッチを制御するlランジスタス
イソチ、S11、S12、S13・・・S1mは第1行
に所属するスイッチ、Snl、 Sn2、SSn3−3
nば第0行に所属するスイッチ、SAI 、SA2、S
A3  ・・・SAmは夫々第1列〜第m列の読み出し
用増幅器、F9〜F12は夫々フリップ・フロップ、S
T′?、Lはセレクタ、MPUはマイクロプロセッサで
ある。
FIG. 1 is a block diagram showing one embodiment of a scanning method according to the present invention. FIG. 2 shows an example of a circuit for reading conventional matrix-type key information. In the figure, Tr ] ~ Tr n i, 1, respectively, 1st row to nth row
l transistors that control the switches belonging to each row, S11, S12, S13...S1m are the switches belonging to the first row, Snl, Sn2, SSn3-3
If n is the switch belonging to the 0th row, SAI, SA2, S
A3...SAm are readout amplifiers for the first to mth columns, respectively, F9 to F12 are flip-flops, and S
T'? , L is a selector, and MPU is a microprocessor.

Claims (1)

【特許請求の範囲】[Claims] 1行に複数m列のキー素子を有するマトリックス形式で
構成されたキー情報を複数mより少ない複数nビット構
成のマイクロプロセッサを使用して読み取る場合、該列
を共通に駆動するトランジスタスイッチを動作させて、
該列に所属するm個の該キー情報の内n個の該キー情報
をセレクタ経由マイクロプロセッサにより読み取り、且
つ残余の該キー情報を(m−n)個のフリップ・フロッ
プに書き込み、次のステップで該セレクタを切り替えて
該(m−n)個のフリップ・フロップに書き込まれたキ
ー情報を該マイクロプロセッサにより読み取ることを特
徴とする走査方式。
When key information configured in a matrix format having a plurality of m columns of key elements in one row is read using a microprocessor having a plurality of n bits less than m, a transistor switch that commonly drives the columns is operated. hand,
Read n pieces of key information out of m pieces of key information belonging to the column by the microprocessor via a selector, write the remaining key information to (m-n) flip-flops, and proceed to the next step. A scanning method characterized in that the microprocessor reads key information written in the (m−n) flip-flops by switching the selector at the (m−n) flip-flops.
JP20123984A 1984-09-26 1984-09-26 Scanning system Pending JPS6179397A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20123984A JPS6179397A (en) 1984-09-26 1984-09-26 Scanning system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20123984A JPS6179397A (en) 1984-09-26 1984-09-26 Scanning system

Publications (1)

Publication Number Publication Date
JPS6179397A true JPS6179397A (en) 1986-04-22

Family

ID=16437640

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20123984A Pending JPS6179397A (en) 1984-09-26 1984-09-26 Scanning system

Country Status (1)

Country Link
JP (1) JPS6179397A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5525251A (en) * 1978-08-10 1980-02-22 Nec Corp Scanning device
JPS5585945A (en) * 1978-12-21 1980-06-28 Mitsubishi Electric Corp Memory unit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5525251A (en) * 1978-08-10 1980-02-22 Nec Corp Scanning device
JPS5585945A (en) * 1978-12-21 1980-06-28 Mitsubishi Electric Corp Memory unit

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