JPS5927941B2 - electronic desk calculator - Google Patents

electronic desk calculator

Info

Publication number
JPS5927941B2
JPS5927941B2 JP9005776A JP9005776A JPS5927941B2 JP S5927941 B2 JPS5927941 B2 JP S5927941B2 JP 9005776 A JP9005776 A JP 9005776A JP 9005776 A JP9005776 A JP 9005776A JP S5927941 B2 JPS5927941 B2 JP S5927941B2
Authority
JP
Japan
Prior art keywords
decimal
hexadecimal
stored
output
switch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP9005776A
Other languages
Japanese (ja)
Other versions
JPS5315727A (en
Inventor
一郎 佐渡
淳 岡田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP9005776A priority Critical patent/JPS5927941B2/en
Publication of JPS5315727A publication Critical patent/JPS5315727A/en
Publication of JPS5927941B2 publication Critical patent/JPS5927941B2/en
Expired legal-status Critical Current

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Description

【発明の詳細な説明】 従来コンピューターに従事する技術者、特にシステムエ
ンジニア、フログラマー等によつて16進演算は不可欠
なものであるが、コンピューターに入力する際、又は出
力後の比較的簡単な16進計算は筆算や暗算に頼つてい
るのが実情で、しばしば計算違いも起す。
DETAILED DESCRIPTION OF THE INVENTION Conventionally, hexadecimal operations have been indispensable for engineers working on computers, especially system engineers, programmer, etc. The reality is that decimal calculations rely on written calculations or mental calculations, which often leads to miscalculations.

本発明はこの点に鑑み、従来の10進電卓に切換えスイ
ッチと簡単なロジックを追加する事により、16進演算
計算機を実現する事を目的としている。
In view of this point, the present invention aims to realize a hexadecimal calculator by adding a changeover switch and simple logic to a conventional decimal calculator.

以下図面に従い詳細な説明を加える。A detailed explanation will be added below according to the drawings.

第1図は本発明の一実施例ブロック図である。FIG. 1 is a block diagram of an embodiment of the present invention.

図中R1、R2はデーター格納レジスタ、ADRIは通
常アダーと呼ばれる16進加算器、ADR2は通常10
進補正回路と呼ばれる加算器、051、052はワンシ
ョット発生回路、SWIは左にすると16進、右にする
と10進の指定を行うスイッチ、CONI、CON2は
ROM(リードオンリーメモリー)ゲート、フリップフ
ロップ等で構成される定数発生及び変換回路G1、G2
、G33G4はアンドゲート、ORIはオアゲート、K
EYはキーボードKBからのキー信号を受け、コード化
する機能、更に詳しく説明すれば置数キー(16進キー
、小数点キー等を含む)を選びコード化してR1に格納
する手段と演算キーを判別してCONTROL部と呼ば
れる演算制御回路部に送る手段とを有している入力制御
部、DISはR2の内容を出力部Dにて表示又は印字す
る為のコントロールである。
In the figure, R1 and R2 are data storage registers, ADRI is a hexadecimal adder usually called an adder, and ADR2 is usually a 10
An adder called a decimal correction circuit, 051 and 052 are one-shot generation circuits, SWI is a switch that specifies hexadecimal when turned to the left, and decimal when turned to the right, CONI and CON2 are ROM (read only memory) gates and flip-flops. Constant generation and conversion circuits G1 and G2 consisting of
, G33G4 is an AND gate, ORI is an OR gate, K
EY has the function of receiving key signals from keyboard KB and encoding them. More specifically, it selects numeric keys (including hexadecimal keys, decimal point keys, etc.), encodes them, and stores them in R1. It determines the means and calculation keys. The input control section DIS is a control for displaying or printing the contents of R2 at the output section D.

第2図は第1図中のCONIをマトリックスで構成した
場合の回路例であり、図中INは10進2桁入力線、F
1〜F80はシリイン・パラアウト(直列入力、並列出
力)のフリップフロップ群でCPIに同期してシフトを
行う。
Figure 2 is an example of a circuit when CONI in Figure 1 is configured as a matrix; IN in the figure is a 2-digit decimal input line;
1 to F80 are series-in/para-out (serial input, parallel output) flip-flops that shift in synchronization with CPI.

IF′1〜1F′80はインバーター、マトリックスの
交点のマルは図に示したダイオード、(又はMOSゲー
ト)F′1〜F′80はパライン、シリアウト(並列入
力、直列出力)のフリップフロップ群でCP2に同期し
てシフトを行う。上記の構成に於て、INに例えば10
進の99が入力されると、F1〜F80に各々1001
1001と格納されマトリックスにより199の入力だ
けが1になり、同時に199の出力はoになる。これよ
りIF′8O、IF′4O、IF’2、[F′1の入力
だけが0になり、インバーターで反転されF1=F2=
F’ 40■ F ′ 80=1、F′ 4■ F’
8■F′10=F′20=0となり、これをCP2でO
UTに導けば16進数C3が出力される。
IF'1 to 1F'80 are inverters, the circles at the intersections of the matrices are the diodes shown in the figure, (or MOS gates) F'1 to F'80 are parallel-line, series-out (parallel input, series output) flip-flops. Shift is performed in synchronization with CP2. In the above configuration, for example, 10
When 99 in decimal is entered, 1001 is entered in F1 to F80 respectively.
It is stored as 1001, and due to the matrix, only the input of 199 becomes 1, and at the same time, the output of 199 becomes o. From this, only the inputs of IF'8O, IF'4O, IF'2, and [F'1 become 0, and are inverted by the inverter, F1=F2=
F' 40■ F' 80=1, F' 4■ F'
8 ■ F'10 = F'20 = 0, which is O at CP2.
When led to UT, hexadecimal number C3 is output.

第3図はCON2を第2図同様のマトリツクス回路で説
明したものであり、[Nより例えば16進数FF(11
11・1111)が入ると、0UTより10進級255
(1001010101)が出力されるものである。以
下いくつかの例題に従い回路動作を説明する。
FIG. 3 illustrates CON2 using a matrix circuit similar to that shown in FIG.
11・1111) is entered, the 10th grade is 255 from 0UT.
(1001010101) is output. The circuit operation will be explained below using some examples.

例1)例1)は 最初SWlを16進にセツトしておき、(5)を置数す
るとR1に5が格納され、次の田によりR1とR2がA
DRlに送られ、R2は0であるから5+O−5がAD
Rlより出力される。
Example 1) In Example 1), SWl is first set to hexadecimal, and when (5) is set, 5 is stored in R1, and by the next field, R1 and R2 are set to A.
Since R2 is 0, 5+O-5 is AD
It is output from Rl.

この時、SWlは16進にセツトされているのでGlO
FFG2ONにより、補正回路ADR2を廻らずにAD
Rlの出力はG2,ORlを介しR2に格納される。次
に(7)キーを押すと7がR1に格納され口キーにより
R1(7)+R2(5)をADRlで実行し、結果はG
2,ORlを介しR2に格納され、16進1100(C
コード)を得る。
At this time, since SWl is set to hexadecimal, GlO
By FFG2ON, AD without going around the correction circuit ADR2.
The output of Rl is stored in R2 via G2 and ORl. Next, when you press the (7) key, 7 is stored in R1, and the mouth key executes R1 (7) + R2 (5) with ADRl, and the result is G.
2, stored in R2 via ORl, hexadecimal 1100 (C
code).

R2はDISに導かれ、Cコードが表示又は印字される
R2 is led to DIS, and the C code is displayed or printed.

この様に16進数相互の演算は従来の10進補正回路を
使用しない事により容易に実現出来る。例2)は SWを16進にセツトしておき、囚を置数するとR1に
格納され、この後SWを10進にセツトすると、ワンシ
ヨツト回路がパルスの立上りつまリスイツチが入つた瞬
間動作するものとすれば0S2が働き、R1の内容がG
4を介しCON2に導かれる。
In this way, calculations between hexadecimal numbers can be easily realized without using the conventional decimal correction circuit. Example 2) sets the SW to hexadecimal, and when a digit is set, it is stored in R1.If the SW is then set to decimal, the one-shot circuit operates at the moment the pulse rises or the reset switch is turned on. Then 0S2 works and the contents of R1 become G
4 to CON2.

CON2では前述の如く16進一10進変換機能を有し
、Aコードを10に変換しR1に格納する。つまりコー
ド1010を10000に変換する。
CON2 has a hexadecimal to decimal conversion function as described above, and converts the A code to 10 and stores it in R1. That is, the code 1010 is converted to 10000.

次に田キーにより10がR2に格納され「キーによりR
1に2が格納され最後の口キーで10+2=12がAD
Rlより出力されSWlは10進にセツトされているの
でG1を介し補正回路に導かれ0R1を介しR2に格納
される。
Next, 10 is stored in R2 by pressing the key, and 10 is stored in R2 by pressing the key.
2 is stored in 1 and 10+2=12 is AD with the last key
Since SWl output from Rl is set to decimal, it is guided to the correction circuit via G1 and stored in R2 via 0R1.

例3)は SWlを10進にセツトしておきnが入力後SWlを1
6進にセツトすると0S1が働きR1がCONlにG3
を介して導かれ、ここで前述の如く10進−16進変換
が行なわれる。
Example 3) sets SWl to decimal, and after n is input, SWl is set to 1.
When set to hexadecimal, 0S1 works and R1 becomes CONl and G3
, where decimal-to-hexadecimal conversion is performed as described above.

例3)ではたまたま10進1桁の例であるが、たとえば
10進の15をCONlに導いても、16進Fコードと
なる。10進9は16進でも9であるから、 9(1001)が再びR1に格納後田により9+0−4
9がR2に格納され、次のE置数でBコードがR1に格
納され、最後の口によりB+9がADRlで実行され、
結果はG2を介しR2に格納され、16進数の答え14
を得る。
Example 3) happens to be an example of a single decimal digit, but even if decimal 15 is led to CONl, it becomes a hexadecimal F code. Since 9 in decimal is also 9 in hexadecimal, 9 (1001) is stored in R1 again and converted to 9+0-4 by Goda.
9 is stored in R2, the next E position stores the B code in R1, the last entry executes B+9 in ADRl,
The result is stored in R2 via G2 and is the hexadecimal answer 14
get.

以上の説明のごとく、スイツチSWlは、10進演算、
16進演算の指定を行うほかに、演算中スイツチを切換
える事により、進数のちがうデーター相互の演算も可能
にしている事がわかる。
As explained above, the switch SWl performs decimal operation,
In addition to specifying hexadecimal calculations, it is also possible to perform calculations on data in different decimal numbers by switching the switch during the calculation.

又、単に演算をしないでデーターの進数変換だけを行う
場合もR1の内容を表示に導くべくCONTLOL部で
制脚すればよい。又、以上3種の例題では、置数直後に
切換えスイツチを動作させて変換を行わしめたが、演算
キーを押した直後で動作させる事もR2を変換回路に導
くか、次の置数の最初でR1のデーターをR2に転送す
るかの方法を選択すれば容易に実現出来る。
Furthermore, even when only converting the data into a base number without performing calculations, the CONTLOL section may be used to guide the contents of R1 to the display. In addition, in the three examples above, the conversion was performed by operating the changeover switch immediately after the input number, but it can also be operated immediately after pressing the calculation key, either by leading R2 to the conversion circuit or by inputting the next input number. This can be easily achieved by first selecting a method of transferring data from R1 to R2.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例のプロツク図、第2,3図は
第1図のCONl,2の詳細図である。
FIG. 1 is a block diagram of one embodiment of the present invention, and FIGS. 2 and 3 are detailed diagrams of CON1 and CON2 in FIG. 1.

Claims (1)

【特許請求の範囲】[Claims] 1 データを格納するレジスタと前記レジスタからのデ
ータが印加される16進加算器と10進補正回路と10
進と16進を手動的に指定するスイッチと前記スイッチ
の指定に従つて前記10進補正回路を使用するか否かを
選択する回路手段とを備えたことを特徴とする電子式卓
上計算機。
1 a register for storing data, a hexadecimal adder to which data from the register is applied, a decimal correction circuit, and a 10
An electronic desktop calculator comprising: a switch for manually specifying decimal and hexadecimal; and circuit means for selecting whether or not to use the decimal correction circuit according to the specification of the switch.
JP9005776A 1976-07-28 1976-07-28 electronic desk calculator Expired JPS5927941B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9005776A JPS5927941B2 (en) 1976-07-28 1976-07-28 electronic desk calculator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9005776A JPS5927941B2 (en) 1976-07-28 1976-07-28 electronic desk calculator

Publications (2)

Publication Number Publication Date
JPS5315727A JPS5315727A (en) 1978-02-14
JPS5927941B2 true JPS5927941B2 (en) 1984-07-09

Family

ID=13987942

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9005776A Expired JPS5927941B2 (en) 1976-07-28 1976-07-28 electronic desk calculator

Country Status (1)

Country Link
JP (1) JPS5927941B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60143041U (en) * 1984-03-05 1985-09-21 市光工業株式会社 auto-dimming mirror

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55121945A (en) * 1979-03-06 1980-09-19 Subaankaa Mukaaji Broardly applicable refractory insulating material
JPS5835658A (en) * 1981-08-25 1983-03-02 Sharp Corp Computer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60143041U (en) * 1984-03-05 1985-09-21 市光工業株式会社 auto-dimming mirror

Also Published As

Publication number Publication date
JPS5315727A (en) 1978-02-14

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