JPS6179260A - High-tension insulated gate type field-effect transistor - Google Patents
High-tension insulated gate type field-effect transistorInfo
- Publication number
- JPS6179260A JPS6179260A JP20092884A JP20092884A JPS6179260A JP S6179260 A JPS6179260 A JP S6179260A JP 20092884 A JP20092884 A JP 20092884A JP 20092884 A JP20092884 A JP 20092884A JP S6179260 A JPS6179260 A JP S6179260A
- Authority
- JP
- Japan
- Prior art keywords
- region
- layer
- channel
- gate
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 title claims description 5
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 239000004065 semiconductor Substances 0.000 claims description 7
- 239000012535 impurity Substances 0.000 claims description 5
- 238000000034 method Methods 0.000 abstract description 12
- 238000005468 ion implantation Methods 0.000 abstract description 7
- 229910052796 boron Inorganic materials 0.000 abstract description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052785 arsenic Inorganic materials 0.000 abstract description 3
- 229910052581 Si3N4 Inorganic materials 0.000 abstract 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 238000007493 shaping process Methods 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 150000004767 nitrides Chemical class 0.000 description 10
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 238000009792 diffusion process Methods 0.000 description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 230000001133 acceleration Effects 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 239000012491 analyte Substances 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- -1 arsenic ions Chemical class 0.000 description 1
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 235000012431 wafers Nutrition 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、高電圧半導体集積回路に用いる高電圧絶縁ゲ
ート型電界効果トランジスタに関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a high voltage insulated gate field effect transistor used in a high voltage semiconductor integrated circuit.
第３図に従来のオフセットゲート型ＭＯ８）ランジスタ
の断面図を示す。同図において、ｌは低不純物濃度（例
えば６ ｘ １０”／ｃｕｔ）のＰ形シリコンよりなる
半導体基板、２はアルミニウムよりなるドレイン電極、
３はソース電極、４は低抵抗多結晶シリコンよりなるゲ
ート電極、５は高濃度Ｎ型領域よりなるドレイン領域、
６はＮ型の低不純物濃度のオフセットゲート領域、１１
は高譲度Ｎ型領域よりなるソース領域である。FIG. 3 shows a cross-sectional view of a conventional offset gate type MO8) transistor. In the figure, l is a semiconductor substrate made of P-type silicon with a low impurity concentration (for example, 6 x 10"/cut), 2 is a drain electrode made of aluminum,
3 is a source electrode, 4 is a gate electrode made of low resistance polycrystalline silicon, 5 is a drain region made of a highly doped N-type region,
6 is an N-type low impurity concentration offset gate region; 11
is a source region consisting of a highly yielding N type region.
第３図の■兇トランジスタは、ドレインをコレクタ、基
板をベース、ソースをエミッタとする寄生バイポーラト
ランジスタが存在し、この寄生バイポーラトランジスタ
がターンオンすることにより、負性抵抗や永久破壊を起
こしたりする欠点がある。■The transistor in Figure 3 has a parasitic bipolar transistor whose drain is the collector, the substrate is the base, and the source is the emitter, and when this parasitic bipolar transistor is turned on, it has the disadvantage of causing negative resistance or permanent damage. There is.
寄生バイポーラトランジスタのターンオンを防止する方
法として、エミッタ接合（ソース−基板間接合）が順バ
イアスされないようにソース直下に基板と同じ導電型の
高濃度層を設け、これをソースと等電位にする方法が提
案されている（特願昭５８−１３０１４３号）。One way to prevent a parasitic bipolar transistor from turning on is to create a highly doped layer of the same conductivity type as the substrate just below the source so that the emitter junction (source-substrate junction) is not forward biased, and make this the same potential as the source. has been proposed (Japanese Patent Application No. 58-130143).
このような原理に基づいた高電圧ＭＯＳトランジスタの
断面構造を第４図に示す。FIG. 4 shows a cross-sectional structure of a high voltage MOS transistor based on such a principle.
この高電圧ＭＯ８）ランジスタでは、同図に示すように
、ソース領域」０の直下に高濃度Ｐ型領域よりなる埋め
込みアース領域９を設け、この埋め込みアース領域９と
、ソース領域ＩＯと、半導体基板ｌの表面とに接して高
濃度Ｐ型領域よりなるアース引き出し領域８が設けられ
、更に、アース引き出し領域８とソース領域ｌＯとが電
気的に接続されている。In this high-voltage MO8) transistor, as shown in the figure, a buried grounding region 9 made of a highly doped P-type region is provided directly under the source region 0, and this buried grounding region 9, the source region IO, and the semiconductor substrate A ground lead-out region 8 made of a highly doped P-type region is provided in contact with the surface of the source region 10, and the ground lead-out region 8 and the source region 1O are electrically connected.
この構造の高電圧ＭＯ８）ランジスタを形成するプロセ
スの一例を第５図を使って説明する。An example of a process for forming a high-voltage MO8) transistor with this structure will be described with reference to FIG.
（ａ） 第５図（ａ）において、半導体基板１に高纒
度のＰ型アース引き出し層８を熱拡散で形成し、次いで
厚さ約１μｍの酸化膜１２を形成した後、窒化膜１３を
形成し、さらにソースとドレインを形成すべき部分の窒
化膜１３の一部を剥離する。(a) In FIG. 5(a), a highly conductive P-type grounding layer 8 is formed on the semiconductor substrate 1 by thermal diffusion, and then an oxide film 12 with a thickness of approximately 1 μm is formed, and then a nitride film 13 is formed. Then, a part of the nitride film 13 where the source and drain are to be formed is peeled off.
（ｂ） 第５図（ｂ）において、フォトレジス） １
４で債化膜１３のドレイン形成領域を選択し、フォトレ
ジスト１４と金化膜１３とをマスクにドレイン形成領域
の酸化膜１２をエツチングする。(b) In Fig. 5(b), photoresist) 1
In step 4, the drain formation region of the bonding film 13 is selected, and the oxide film 12 in the drain formation region is etched using the photoresist 14 and the gold film 13 as a mask.
（ｅ） 第５図（Ｃ）において、高濃度のＮ型ドレイ
ン領域５を熱拡散で形成する。次いでフォトレジス）
１５で窒化膜１３のソース形成領域を選択し、フォトレ
ジスト１５と窒化膜１３とをマスクとしてソース領域の
酸化膜１２をエツチングする。(e) In FIG. 5C, a highly doped N-type drain region 5 is formed by thermal diffusion. then photoregis)
In step 15, a source formation region of the nitride film 13 is selected, and the oxide film 12 in the source region is etched using the photoresist 15 and the nitride film 13 as a mask.
（ｄ） 第５図（ｄ）において、同ソース領域に形成
された開口部を通してイオン注入法により、ボロンと砒
素とを打ち込み、埋め込みアース領域９とソース領域１
０を形成する・
以下、Ｎ型の低不純物濃度領域よりなるオフセットゲー
ト部を形成し、更にシリコンゲートを形成して、第４図
に示した高電圧ＮＭＯ８）ランジスタが完成する。(d) In FIG. 5(d), boron and arsenic are implanted by ion implantation through the opening formed in the same source region, and the buried earth region 9 and source region 1 are implanted.
After that, an offset gate portion consisting of an N-type low impurity concentration region is formed, and a silicon gate is further formed to complete the high voltage NMO transistor 8) shown in FIG.
以上の高電圧ＮＭＯ８）ランジスタプロセスにおいては
、埋め込みアース領域９を形成する為に（ｄ）の工程で
ボロンを高加速エネルギー、高ドーズ甘（例えば１５０
ＫａＶで５ ｘ １０”／ｃｉｌ）で打ち込む必要が
ある。このとき酸化膜１２と窒化膜１３とがイオン注入
のマスクとして作用するが、十分なマスク作用を得るに
は併せて、約１μｍの厚さが必要である。In the above high-voltage NMO transistor process (8), in order to form the buried ground region 9, boron is used at a high acceleration energy and a high dose (for example, 150%) in the step (d).
The oxide film 12 and the nitride film 13 act as a mask for ion implantation, but in order to obtain a sufficient masking effect, a thickness of approximately 1 μm is required. It is necessary to
埋め込みアース領域９を形成するためこの厚い酸化膜１
２は（ｅ）の工程でエツチングされ、酸化膜１２が厚い
分だけサイドエッチが入る（第１のサイドエッチ）。そ
のうえソース領域ＩＯを砒素のイオン打ち込みで形成す
る前に埋め込みアース領域９からのボロンの横広がりに
よりしきい値電圧が大きくなるのを避ける為に酸化膜に
対して約５ 、０００人のサイドエッチを行なわれる（
第２のサイドエッチ）。This thick oxide film 1 is used to form a buried ground region 9.
2 is etched in the step (e), and a side etch is made by the thickness of the oxide film 12 (first side etch). Furthermore, before forming the source region IO by arsenic ion implantation, the oxide film is side-etched by approximately 5,000 wafers in order to prevent the threshold voltage from increasing due to the lateral spread of boron from the buried ground region 9. will be carried out (
2nd side etch).
ところで、第４図に示された高電圧ＮＭＯ８）ランジス
タのチャンネル長は、ソース領域ｌＯとオフセットゲー
ト部６との長さで決定されるが、上述の２つのサイドエ
ッチ量が大きく、またバラツキも大きいため、所望のチ
ャンネル長を得ることはむずかしく、チャンネル長のバ
ラツキが太きくなるという問題があった。By the way, the channel length of the high voltage NMO transistor 8) shown in FIG. Since the channel length is large, it is difficult to obtain a desired channel length, and there is a problem in that the variation in channel length increases.
本発明の目的は、上述の欠点を取り除き、チャンネル長
にバラツキがなく、しかも短チャンネルの絶縁ゲート型
電界効果トランジスタを提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks and provide an insulated gate field effect transistor having a uniform channel length and a short channel.
本発明は一導電型の半導体基板の一主面に設けられた逆
導電型のソース領域及びドレイン領域と、該ドレイン領
域に接して設けられた逆導電型のオフセットゲート領域
と、該オフセットゲート領域及び前記ソース領域間に形
成されるチャンネル領域とを有する絶縁ゲート型電界効
果トランジスタにおいて、前記ソース領域に接して該ソ
ース領域と、前記チャンネル領域との間にオフセットゲ
ート領域と同じ導電型不純物嬢度の低濃度ソース領域を
設け、前記低濃度ソース領域と前記チャンネル領域とに
またがり、絶縁膜を介してゲートを形成し、前記低濃度
ソース領域上の絶縁膜を前記チャンネル領域上の絶縁膜
より薄くしたことを特徴とする高電圧絶縁ゲート型電界
効果トランジスタである。The present invention includes a source region and a drain region of opposite conductivity type provided on one main surface of a semiconductor substrate of one conductivity type, an offset gate region of opposite conductivity type provided in contact with the drain region, and the offset gate region. and a channel region formed between the source regions, wherein an impurity of the same conductivity type as the offset gate region is provided between the source region and the channel region in contact with the source region. a low concentration source region is provided, a gate is formed across the low concentration source region and the channel region through an insulating film, and the insulating film on the low concentration source region is thinner than the insulating film on the channel region. This is a high voltage insulated gate field effect transistor characterized by the following characteristics.
以下に本発明の実施例について図面を６照して詳細に説
明する。Embodiments of the present invention will be described in detail below with reference to the drawings.
第１図に本発明の高電圧ＮＭＯ８）ランジスタの断面構
造図を示す。FIG. 1 shows a cross-sectional structural diagram of a high voltage NMO8) transistor of the present invention.
ｌは、例えば６×１０１４／ｃｄのＰ型シリコン基板で
ある。２はドレイン電極、３はソ、−ス電極、４は多結
晶シリコンよりなるゲート電極、５は高濃度のＮ型ソー
ス領域、６はオフセットゲート領域、７は低濃度ソース
領域である。l is, for example, a P-type silicon substrate of 6×10 14 /cd. 2 is a drain electrode, 3 is a source electrode, 4 is a gate electrode made of polycrystalline silicon, 5 is a heavily doped N-type source region, 6 is an offset gate region, and 7 is a lightly doped source region.
ここでオフセットゲート領域６と低濃度ソース領域７と
は従来の工程のオフセットゲート形成時に同時に形成さ
れたものである。８は高濃度Ｐ型の引き出しアース拡散
領域、９は高加速エネルギー高ドーズ量のボロンイオン
注入による埋め込みアース拡散領域である。ｌＯは高加
速エネルギー高ドーズ量の砒素イオン注入によるソース
領域である。１６は５００人程程度酸化膜、１７は１３
００人の酸化膜である。Here, the offset gate region 6 and the low concentration source region 7 are formed at the same time when the offset gate is formed in a conventional process. Reference numeral 8 designates a highly-concentrated P-type drawn-out ground diffusion region, and reference numeral 9 designates a buried ground diffusion region formed by boron ion implantation with high acceleration energy and high dose. IO is a source region formed by implanting arsenic ions at high acceleration energy and high dose. 16 is an oxide film of about 500 people, 17 is 13
00 people's oxide film.
第２図の（ａ）〜（ｃ）に本発明の形成法の一例を示す
。An example of the formation method of the present invention is shown in FIGS. 2(a) to 2(c).
なお、埋め込みアース領域、ソース領域形成工程までは
、第５図（ａ）〜（ｄ）に示した従来構造のトランジス
タの成形工程と同一である。Incidentally, the process up to the process of forming the buried ground region and the source region is the same as the process of forming the transistor of the conventional structure shown in FIGS. 5(a) to 5(d).
（ａ） 第２図（ａ）において、表面に５００人の酸
化、［１６を形成した後、５００人の窒化膜１８を形成
する・次いでフォトレジスト１９をマスクとして、イオ
ン注入法によりオフセットゲート領域６と低濃度ソース
領域７とを形成する。(a) In FIG. 2(a), after forming 500 layers of oxidation film 16 on the surface, 500 layers of nitride film 18 is formed.Next, using photoresist 19 as a mask, ion implantation is performed to form an offset gate region. 6 and a low concentration source region 7 are formed.
（ｂ） 第２図（ｂ）において、低嬢度領域７の部分
にのみ窒化膜１８を残し、他は剥離する。次にチャンネ
ル領域２０及びオフセットゲート部領域６上に、膜厚が
ｘ、ａｏｏＡのゲート酸化ｆｉ１７を形成する。(b) In FIG. 2(b), the nitride film 18 is left only in the low resistance region 7, and the rest is peeled off. Next, a gate oxide fi17 having a film thickness of x and aooA is formed on the channel region 20 and the offset gate region 6.
（ｃ） 第２図（ｅ）において、窒化膜１８を剥離し
、低濃度ソース領域と、チャンネル領域とにまたがって
多結晶シリコンゲート４を形成する。これにより低濃度
ソース領域７上に形成されるシリコンゲート４下の絶縁
膜１６ ｋチャンネル領域２０上のゲート４下の絶縁膜
１７より薄くなり、第１図に示した尚電圧ＮＭＯ８）ラ
ンジスタを完成する。(c) In FIG. 2(e), the nitride film 18 is peeled off, and a polycrystalline silicon gate 4 is formed spanning the low concentration source region and the channel region. As a result, the insulating film 16 under the silicon gate 4 formed on the low concentration source region 7 becomes thinner than the insulating film 17 under the gate 4 on the k channel region 20, completing the voltage NMO transistor shown in FIG. do.
ここでチャンネル長ＬＥはオフセットゲート領域６と低
＃Ｉ！Ｉｆソース領域７との長さにより決定され、ソー
ス領域形成の際のナイドエッチ量とは無関係である。そ
のため所望通りのチャンネル長が形成できる。Here, the channel length LE is the offset gate region 6 and the low #I! If, it is determined by the length of the source region 7, and is unrelated to the amount of nide etching when forming the source region. Therefore, a desired channel length can be formed.
又、ドレインゲート間の耐圧を高くするためにオフセッ
トゲート部上の絶縁膜は１．３０ＯＡ程反必要である。Further, in order to increase the withstand voltage between the drain and gate, the insulating film on the offset gate portion needs to have a thickness of about 1.30 OA.
一方、ソース−ゲート間に印加される電圧は高々ｌＯｖ
程度であり、低濃度ソース領域７上の酸化膜（絶縁膜）
１６は厚くする必要がない。本実施例の場合、サイドエ
ッチ量の影響を無視するためには、低濃度領域層の長さ
は３μｍ以上必要であり、この部分の抵抗は無視できな
くなる。そこで抵抗を減らすためには、低濃度領域層上
の酸化膜厚を薄くしなければならない０本実施例ではこ
の膜厚を５００にの厚さに設定したところ、従来の高電
圧トランジスタに比べ電流特性の優れたトランジスタが
得られた。On the other hand, the voltage applied between source and gate is at most lOv
The oxide film (insulating film) on the low concentration source region 7
16 does not need to be thick. In the case of this embodiment, in order to ignore the influence of the side etching amount, the length of the low concentration region layer needs to be 3 μm or more, and the resistance of this portion cannot be ignored. Therefore, in order to reduce the resistance, it is necessary to reduce the thickness of the oxide film on the low concentration region layer. In this example, when this film thickness was set to 500%, the current A transistor with excellent characteristics was obtained.
本発明は、低濃度ソース領域とオフセットゲート領域と
を同時に形成するため、両者の間の距離即ちチャンネル
長を一義的に決めることができ、チャンネル長のバラツ
キを非常に小さく又短チャンネルも容易に形成できる。In the present invention, since the low concentration source region and the offset gate region are formed at the same time, the distance between them, that is, the channel length, can be uniquely determined, and the variation in channel length can be minimized and short channels can be easily formed. Can be formed.
さらに、低濃度ソース領域には薄い絶縁膜を介してゲー
トを重ねるため、チャンネルがオンになる極性の電位が
ゲートに加わると低濃度ソース領域の抵抗は著しく小さ
くなり、従って低濃度ソース領域の影響でトランジスタ
のドレイン抵抗が大きくなるといった不都合は生じない
。Furthermore, since the gate is stacked on the low-concentration source region via a thin insulating film, when a polar potential that turns on the channel is applied to the gate, the resistance of the low-concentration source region becomes significantly small. Therefore, the disadvantage that the drain resistance of the transistor becomes large does not occur.
したがって、本発明によれば、短チャンネルの高電圧Ｎ
ＭＯ８）ランジスタを信頼性よく形成でき、しかも検体
がりの少ないイオン注入法によりチャンネル長を決定で
きるので所望の値が得られ、プロセスは通常のＣＭＯＳ
プロセスと適合性があるので容易に形成できる効果を有
するものである。Therefore, according to the invention, the short channel high voltage N
MO8) Transistors can be formed with high reliability, and the channel length can be determined by ion implantation with less analyte scatter, so the desired value can be obtained, and the process is similar to that of ordinary CMOS.
Since it is compatible with the process, it has the effect of being easily formed.
第１図１１本発明の実施例を示す高電圧ＮＭＯ８）ラン
ジスタの断面図、第２図（ａ）〜（ｅ）は本発明の形成
力法の一例を工程順に示す断面図、第３図は従来の高電
圧ＮＭＯ８）ランジスタの断面図、第４図は耐負性抵抗
、耐永久破壊防止対策のある従来の高電圧ＮＭＯ８）ラ
ンジスタの断面図、第５図（ａ）〜（ａは第４図に示さ
れた高電圧ＮＭＯ８）ランジスタの製造工程を工程順に
示す断面図である。
ｌ・・・半導体基板、２・・・ドレイン電極、３・・・
ソース電極、４・・・ポリシリコン’ｙ−）、５・・・
ソース領域、６・・・オフセットゲート領域、７・・・
チャンネル位置決め領域、８・・・引き出しアース拡散
領域、９・・・埋め込みアース領域、１０ 、１１・・
・ソース領域、１２・・・酸化膜、１３・・・窒化膜、
１４ 、１５・・・フォトレジスト、１６・・・薄い酸
化膜、１７・・・ゲートシリコン酸化膜、１８・・・窒
化膜、１９・・・フォトレジスト、２０・・・チャンネ
ル領域
特許出願人 日本電気株式会社
第２図
（ｂ、）
（Ｃ）
第３図
第４図
第５図
（ｂ）
第ろ図
（ｄ）FIG. 1 is a cross-sectional view of a high-voltage NMO8) transistor showing an embodiment of the present invention, FIGS. 2(a) to (e) are cross-sectional views showing an example of the forming force method of the present invention in the order of steps, A cross-sectional view of a conventional high-voltage NMO8) transistor, Figure 4 is a cross-sectional view of a conventional high-voltage NMO8) transistor with negative resistance and permanent damage prevention measures, and Figures 5(a) to (a are Figure 4) FIG. 8 is a cross-sectional view illustrating the manufacturing process of the high-voltage NMO8) transistor shown in FIG. l...Semiconductor substrate, 2...Drain electrode, 3...
Source electrode, 4... polysilicon 'y-), 5...
Source region, 6... Offset gate region, 7...
Channel positioning area, 8... Leading out grounding diffusion area, 9... Embedded grounding area, 10, 11...
- Source region, 12... oxide film, 13... nitride film,
14, 15... Photoresist, 16... Thin oxide film, 17... Gate silicon oxide film, 18... Nitride film, 19... Photoresist, 20... Channel region patent applicant Japan Denki Co., Ltd. Figure 2 (b,) (C) Figure 3 Figure 4 Figure 5 (b) Figure 5 (d)
Claims (1)
電型のソース領域及びドレイン領域と、該ドレイン領域
に接して設けられた逆導電型のオフセットゲート領域と
、該オフセットゲート領域及び前記ソース領域間に形成
されるチャンネル領域とを有する絶縁ゲート型電界効果
トランジスタにおいて、前記ソース領域に接して該ソー
ス領域と前記チャンネル領域との間に、オフセットゲー
ト領域と同じ導電型不純物濃度の低濃度ソース領域を設
け、前記低濃度ソース領域と前記チャンネル領域上とに
またがつて絶縁膜を介してゲートを形成し、低濃度ソー
ス領域上の絶縁膜を前記チャンネル領域上の絶縁膜より
薄くしたことを特徴とする高電圧絶縁ゲート型電界効果
トランジスタ。(1) A source region and a drain region of opposite conductivity type provided on one main surface of a semiconductor substrate of one conductivity type, an offset gate region of opposite conductivity type provided in contact with the drain region, and the offset gate region and a channel region formed between the source regions, in which an impurity concentration of the same conductivity type as that of the offset gate region is provided between the source region and the channel region in contact with the source region. A low concentration source region is provided, a gate is formed across the low concentration source region and the channel region via an insulating film, and the insulating film on the low concentration source region is thinner than the insulating film on the channel region. A high voltage insulated gate field effect transistor characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20092884A JPS6179260A (en) | 1984-09-26 | 1984-09-26 | High-tension insulated gate type field-effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20092884A JPS6179260A (en) | 1984-09-26 | 1984-09-26 | High-tension insulated gate type field-effect transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6179260A true JPS6179260A (en) | 1986-04-22 |
Family
ID=16432612
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20092884A Pending JPS6179260A (en) | 1984-09-26 | 1984-09-26 | High-tension insulated gate type field-effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6179260A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5304827A (en) * | 1991-10-15 | 1994-04-19 | Texas Instruments Incorporated | Performance lateral double-diffused MOS transistor |
-
1984
- 1984-09-26 JP JP20092884A patent/JPS6179260A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5304827A (en) * | 1991-10-15 | 1994-04-19 | Texas Instruments Incorporated | Performance lateral double-diffused MOS transistor |
| US5382535A (en) * | 1991-10-15 | 1995-01-17 | Texas Instruments Incorporated | Method of fabricating performance lateral double-diffused MOS transistor |
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