JPS6177390A - Circuit board - Google Patents
Circuit boardInfo
- Publication number
- JPS6177390A JPS6177390A JP59198466A JP19846684A JPS6177390A JP S6177390 A JPS6177390 A JP S6177390A JP 59198466 A JP59198466 A JP 59198466A JP 19846684 A JP19846684 A JP 19846684A JP S6177390 A JPS6177390 A JP S6177390A
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- circuit board
- conductive film
- circuit element
- stepped portion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Landscapes
- Die Bonding (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、集積回路素子を搭載せる回路基板に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a circuit board on which integrated circuit elements are mounted.
集積回路をパッケージ内に収納した集積回路素子におい
ては、摩擦などによってパッケージに静電荷が生じやす
く、この静電荷が多量生じたことによって放電が生ずる
と、集積回路が破壊されるおそれがある。また、外部か
らの雑音などが集積回路に影響し、たとえばこの集積回
路がＣＰＵである場合、とのＣＰＵが誤動作してしまう
。In an integrated circuit device in which an integrated circuit is housed in a package, static charges are likely to be generated in the package due to friction or the like, and if a large amount of this static charge is generated and discharge occurs, the integrated circuit may be destroyed. In addition, external noise affects the integrated circuit, and if this integrated circuit is a CPU, for example, the CPU may malfunction.
このために、従来、かかる集積回路素子を回路基板の基
板本体に載置する場合、第５図に示すように、基板本体
４上に導電パターンとして形成された接地線６に導電性
接着剤５でもって集積回路素子１を接着し、この集積回
路素子１に設けられた電極（図示せず）と導電パターン
として形成された信号線３とをワイヤ２でもってボンデ
ィングしている。For this reason, conventionally, when mounting such an integrated circuit element on the main body of a circuit board, as shown in FIG. The integrated circuit element 1 is thereby bonded, and the wire 2 is used to bond an electrode (not shown) provided on the integrated circuit element 1 to a signal line 3 formed as a conductive pattern.
このために、集積回路素子１は導電性接着剤５を介して
接地線６に接続され、パッケージ後に生ずる静電気を接
地線６ににがすことかできるとともに、回路基板が集積
回路素子１のシールド板として作用することとなり、外
部雑音や静電気による影響を防止することができる。For this purpose, the integrated circuit element 1 is connected to the ground wire 6 via the conductive adhesive 5, and the static electricity generated after packaging can be transferred to the ground wire 6. It acts as a board and can prevent the effects of external noise and static electricity.
ところで、回路基板としては、第５図に示すように、平
坦な基板本体に集積回路素子を搭載するようにした捻か
に、第６図に示すように、基板本体４に段差部７を設け
、この段差部７に集積回路素子１を設けるようにした回
路基板も従来知られている。かかる回路基板は、たとえ
ばカード本体に集積回路化されたマイクロコンピュータ
やメモリなどの集積回路素子を取りつけ、データの処理
や記憶を可能としたカード（ＩＣカード）などに利用さ
れる。すなわち、このＩＣカードは、集積回路素子が搭
載された回路基板をカード本体に設けたくほみに嵌め込
み、そのＩＣカードの厚みをカード本体の厚みに 等し
くて携帯に便利なようにしており、・このために、集積
回路素子も回路基板の表面から突出しないようにする必
要がある。By the way, as a circuit board, as shown in FIG. 5, integrated circuit elements are mounted on a flat board body, and as shown in FIG. 6, a stepped portion 7 is provided on the board body 4. A circuit board in which an integrated circuit element 1 is provided in the stepped portion 7 is also known. Such a circuit board is used, for example, in a card (IC card) in which an integrated circuit element such as an integrated circuit microcomputer or memory is attached to a card body to enable data processing and storage. In other words, in this IC card, a circuit board on which an integrated circuit element is mounted is fitted into a hole provided in the card body, and the thickness of the IC card is equal to the thickness of the card body, making it convenient to carry. For this reason, it is necessary that the integrated circuit elements also not protrude from the surface of the circuit board.
そこで、かかるＩＣカードには、第６図に示すような回
路基板が適していることになるが、かかる回路基板は、
通常、信号線３や接地線（図示せず）の導電パターンが
形成された上基板４１に貫通孔を設け、さらに、この上
基板４１に下基板４２を貼り合わせてくぼみ部７を形成
し、このくぼみ部７の底面（下基板４．の表面）に接着
剤８でもって集積回路素子１を接着する。Therefore, a circuit board as shown in FIG. 6 is suitable for such an IC card.
Usually, a through hole is provided in an upper substrate 41 on which conductive patterns for signal lines 3 and ground lines (not shown) are formed, and a lower substrate 42 is bonded to this upper substrate 41 to form a recessed portion 7. The integrated circuit element 1 is adhered to the bottom surface of the recessed portion 7 (the surface of the lower substrate 4) using an adhesive 8.
このように、この回路基板では、導電パターンが形成さ
れた上基板４１の一部を打抜いてくぼ木部７を形成する
ようにしたものであるから、くぼみ部７には、接地線が
設けられず、したがって、第５図に示したように、集積
回路素子１を導電性接着剤５でもって接地線に接着させ
るようなことはできない。As described above, in this circuit board, a part of the upper substrate 41 on which the conductive pattern is formed is punched out to form the recessed wooden part 7, so a grounding wire is provided in the recessed part 7. Therefore, it is not possible to bond the integrated circuit element 1 to the ground wire with the conductive adhesive 5 as shown in FIG.
段差部が基板本体の導電パターンが施こされた面から突
出している回路基板についても同様である。The same applies to a circuit board in which the stepped portion protrudes from the surface of the board body on which the conductive pattern is applied.
本発明の目的は、上記従来技術の問題点Ｙ解消し、基板
本体に設けた段差部に載置された集積回路素子を容易に
接地することができるようにした回路基板を提供するに
ある。SUMMARY OF THE INVENTION An object of the present invention is to provide a circuit board that solves the above-mentioned problems of the prior art and allows easy grounding of integrated circuit elements mounted on a stepped portion provided on a board body.
このために、本発明は、導電性接着剤でもって集積回路
素子を段差部の表面に接着するとともに、該段差部の側
面に導電膜を設け、該集積回路素子を該導電性接着剤と
骸導電膜を介して基板本体に形成された接地線に接続で
きるようにしたものである。To this end, the present invention adheres the integrated circuit element to the surface of the stepped portion using a conductive adhesive, provides a conductive film on the side surface of the stepped portion, and attaches the integrated circuit element to the surface of the stepped portion using the conductive adhesive. It is designed so that it can be connected to a ground line formed on the substrate body via a conductive film.
以下、本発明の実施例を図面を用いて説明する。 Embodiments of the present invention will be described below with reference to the drawings.
第１図は本発明による回路基板の一実施例を示し、同図
（ａ）はその斜視図、同図（ｂ）は同図（ａ）の分断線
Ａ−ＡＫ沿う断面図である。また、第１図（ａ）。FIG. 1 shows an embodiment of a circuit board according to the present invention, and FIG. 1(a) is a perspective view thereof, and FIG. 1(b) is a sectional view taken along the dividing line A-AK in FIG. 1(a). Also, FIG. 1(a).
（ｂ）において、９は側面、１０は導電膜であり、第５
図および第６図に対応する部分には同一符号をつけてい
る。In (b), 9 is a side surface, 10 is a conductive film, and the fifth
Portions corresponding to those in the figure and FIG. 6 are given the same reference numerals.
この実施例においては、段差部をくぼみとする。In this embodiment, the stepped portion is a depression.
第１図（ａＬ （ｂ）において、第６図で説明したよう
に、信号線３（１つだけに符号をつけている）、接地線
６の導電パターンが施こされた上基板４．の一部を打抜
き、これに下基板４□を接着することにより、基板本体
４にくぼみ部７が形成されている。In FIG. 1(aL(b)), as explained in FIG. A recessed portion 7 is formed in the substrate body 4 by punching out a portion and adhering the lower substrate 4□ thereto.
このくぼみ部７の底面には、導電性接着剤５でもって集
積回路素子１が接着されており、この集積回路素子１の
各端子と所定の信号＃３と間がワイヤ２（１つだけ符号
をつけている）でボンディングされている。An integrated circuit element 1 is adhered to the bottom surface of the recessed part 7 with a conductive adhesive 5, and wires 2 (only one is marked ) is bonded.
くぼみ部７の１つの側面９には、上基板４、の表面から
くぼみ部７の底面まで導電膜１０が施こされ、この導電
膜１０の一端は接地線６に接続されている。また、集積
回路素子１をくぼみ部７に接着する導電性接着剤５は、
導電膜１０の他端に達するように、集積回路素子室の底
部から延びてくぼみ部７の底面に塗布されている。A conductive film 10 is formed on one side surface 9 of the recess 7 from the surface of the upper substrate 4 to the bottom of the recess 7 , and one end of the conductive film 10 is connected to the ground line 6 . Furthermore, the conductive adhesive 5 for bonding the integrated circuit element 1 to the recessed portion 7 is
It extends from the bottom of the integrated circuit element chamber and is applied to the bottom surface of the recess 7 so as to reach the other end of the conductive film 10 .
そこで、集積回路素子１のパッケージは、導電性接着剤
５．導電膜１０を介して接地＠６に接続される。このた
めに、このパッケージは接地されることになり、外部雑
音に対するシールドとして作用するとともに、パッケー
ジでの静電気の発生を防止できる。Therefore, the package of the integrated circuit element 1 is made of conductive adhesive 5. It is connected to ground @6 via the conductive film 10. Therefore, this package is grounded, which acts as a shield against external noise and prevents static electricity from being generated in the package.
導電膜１０としては、導電性接着剤５と同じ、たとえば
、銀あるいは銅などを含むエポキシ樹脂などの接着剤を
側面９に塗布あるいは上から垂らすことによって形成す
ることができるし、金、銅などの金属メッキによって形
成することもできる。The conductive film 10 can be formed by applying the same adhesive as the conductive adhesive 5, such as an epoxy resin containing silver or copper, to the side surface 9 or dropping it from above. It can also be formed by metal plating.
また、下基板４２を貼り合わせる前に上基板４．に前記
の細工をしてもよい。導電膜１０の厚さは、１０〜５０
ｐｍが適当である。Also, before bonding the lower substrate 42 together, the upper substrate 4. The above-mentioned modification may be applied to the The thickness of the conductive film 10 is 10 to 50
pm is appropriate.
なお、上基板４８，４□は夫々厚さ０．４ｍ＋、 ０
．１＋ｅ＋とじ、ともに熱硬化性樹脂であるビスマレイ
ミドトリアジン樹脂を用いた。しかし、ガラスエポキシ
やセラミックなどの絶縁基板を用いることもできる。、
また、集積回路素子としては、Ｉｌ横夫々５簡で厚さ０
．４ ｍのものを用い、くぼみ部７としては、縦横夫々
６ｍとした。Note that the upper substrates 48, 4□ have a thickness of 0.4 m+, 0
．． 1+e+ binding, both using bismaleimide triazine resin, which is a thermosetting resin. However, an insulating substrate such as glass epoxy or ceramic may also be used. ,
In addition, as an integrated circuit element, the Il width is 5 strips each and the thickness is 0.
．． A 4 m long piece was used, and the recessed portion 7 was 6 m in length and width.
第２図は本発明による回路基板の他の実施例を示し、同
図（ａ）はその斜視図、同図（ｂ）は同図（ａ）の分断
線Ａ−ＡＫ沿う断面図である。また、第２図（ａ）。FIG. 2 shows another embodiment of the circuit board according to the present invention, and FIG. 2(a) is a perspective view thereof, and FIG. 2(b) is a sectional view taken along the dividing line A-AK in FIG. 2(a). Also, FIG. 2(a).
（１））において、１）は溝部であり、第１図に対応す
る部分には同一符号をつけて重複する説明は省略する。In (1)), 1) is a groove portion, and portions corresponding to those in FIG. 1 are given the same reference numerals and redundant explanations will be omitted.
第１図に示した実施例は、くぼみ部７の側面に、導電性
接着剤を塗布あるいは垂らすことにより、また、金属メ
ッキにより、導電膜１０を形成したが、第２図に示すこ
の実施例では、くぼみ部７の側面に、上基板４、の接地
線６が設けられた表面からくぼみ部９の底面（下基板４
２の表面）まで溝部１）を形成し、この溝部に導電ｍ１
０が形成されているものである。これ以外の点について
は、第１図に示した実施例と同様である。In the embodiment shown in FIG. 1, the conductive film 10 was formed by applying or dropping a conductive adhesive on the side surface of the recess 7 or by metal plating, but in this embodiment shown in FIG. Now, from the surface where the ground wire 6 of the upper substrate 4 is provided on the side surface of the recessed portion 7, to the bottom surface of the recessed portion 9 (lower substrate 4
2), and conductive m1 is formed in this groove.
0 is formed. Other points are the same as the embodiment shown in FIG.
かかる基板本体４は、第３図に示すように、信号線３．
接地線６などの導体パターンが施こされた上基板４．に
スルーホール１２を設け、このスルーホール１２内の導
体が接地＋ｖ！６に接続されるようにし、しかる後、こ
のスルーホール１２の桔、断面の半分程度がかかるよう
に、点線で示す所定の領域を打抜き、さら゛に、下基板
４□を接着するととによって得られる。この打抜きによ
り、このスルーホール１２は内部が露出して算２図（ａ
）に示す溝部１）となり、このスルーホール１２に設け
た導体が第２図（ａ）に示す導電膜となる。スルーホー
ル１２の直径は０．２〜２．０ ｍ程度とした。As shown in FIG. 3, this board main body 4 has signal lines 3.
An upper substrate 4 on which a conductor pattern such as a grounding wire 6 is formed. A through hole 12 is provided in the through hole 12, and the conductor inside this through hole 12 is grounded +v! 6, and then punch out a predetermined area shown by dotted lines so that about half of the cross section of this through hole 12 is covered, and then glue the lower substrate 4□. It will be done. Due to this punching, the inside of this through hole 12 is exposed and
), and the conductor provided in this through hole 12 becomes the conductive film shown in FIG. 2(a). The diameter of the through hole 12 was approximately 0.2 to 2.0 m.
以上の実施例は、一部を打抜いた上基板と平坦な下基板
とを貼り合わせることにより、基板本体にくぼみ部を形
成するものであったが、第４図に示すように、１板の厚
目の基板本体を用い、その一部を座ぐりなどＫよって削
りとり、くほみ部を形成するようにしてもよい。In the above embodiment, a recessed portion is formed in the substrate body by pasting together a partially punched upper substrate and a flat lower substrate, but as shown in FIG. A thick substrate body may be used, and a portion thereof may be cut off with a counterbore or the like to form a recessed portion.
なお、上記実施例は、段差部がくぼみ部であったが、突
出部であってもよい。また、上記夫々の数値は一例を示
すものであって、本発明がこれらの数値によって限定さ
れるものではない。In the above embodiment, the stepped portion is a recessed portion, but it may be a protruding portion. Moreover, each of the above-mentioned numerical values shows an example, and the present invention is not limited to these numerical values.
以上説明したように、本発明によれば、基板本体の段差
部に載置された集積回路素子と接地線とを容易にかつ確
実に接続することができ、該集積回路素子のパッケージ
にシールド作用をもたせることができるとともに、該パ
ッケージでの静電気の発生を防止できるものであって、
上記従来技術の問題点を解消して優れた機ａＰの回路基
板を伊供することができる。As explained above, according to the present invention, it is possible to easily and reliably connect the integrated circuit element placed on the stepped portion of the substrate body to the ground wire, and to provide a shielding effect on the package of the integrated circuit element. and can prevent the generation of static electricity in the package,
By solving the problems of the prior art described above, it is possible to provide an excellent aP circuit board.
１）図（ａ）は本発明による回路基板の一実施例を示す
斜視図、躯１図（ｂ）は１）図（ａ）の分断線Ａ−Ａに
沿う断面図、第２図（ａ）は本発明による回路基板の他
の実施例を示す斜視図、鎖２図（ｂ）は第２図（ａ）の
分断線Ａ−Ａに沿う断面図、卯２３図は第２図（ａ）。
（ｂ）に示すくぼみ部の形成方法の一具体例を示す説明
図、第４図は本発明による回路基板のさらに他の実施例
を示す断面図、詑５図および第６図は夫々回路基板の従
来例を示す断面図である。
１・・・・・・集積回路素子、４・・・・基板本体、５
・・・・・導電性接着剤、６・・・・・・接地線、７・
・・・・・＜ Ｉｉみ部、９・・・・・・側面、１０・
・・・・導を膜、１）・・・・・・溝部。1) Figure (a) is a perspective view showing an embodiment of the circuit board according to the present invention, Figure 1 (b) is a cross-sectional view taken along the dividing line A-A in Figure (a), and Figure 2 (a) ) is a perspective view showing another embodiment of the circuit board according to the present invention, Figure 2 (b) is a sectional view taken along the dividing line A-A in Figure 2 (a), and Figure 23 is a perspective view showing another embodiment of the circuit board according to the present invention. ). (b) is an explanatory diagram showing a specific example of the method for forming the recessed portion, FIG. 4 is a sectional view showing still another embodiment of the circuit board according to the present invention, and FIGS. FIG. 2 is a sectional view showing a conventional example. 1... Integrated circuit element, 4... Board body, 5
... Conductive adhesive, 6 ... Ground wire, 7.
...< Ii corner, 9... Side, 10.
... Conductive film, 1) ... Groove.
Claims (4)
置された回路基板において、該集積回路素子を導電性接
着剤によつて該段差部の表面に接着するとともに、該段
差部の側面に導電膜を設け、該導電性接着剤および該導
電膜を介して該集積回路素子を接地可能に構成したこと
を特徴とする回路基板。(1) In a circuit board provided with a stepped portion and an integrated circuit element mounted on the stepped portion, the integrated circuit element is adhered to the surface of the stepped portion with a conductive adhesive, and 1. A circuit board comprising: a conductive film provided on a side surface of the integrated circuit element; and a conductive film configured to allow the integrated circuit element to be grounded via the conductive adhesive and the conductive film.
を導電性接着剤で形成したことを特徴とする回路基板。(2) A circuit board according to claim (1), characterized in that the conductive film is formed of a conductive adhesive.
を金属メッキ膜で形成したことを特徴とする回路基板。(3) The circuit board according to claim (1), wherein the conductive film is formed of a metal plating film.
は前記段差部の前記表面から前記側面に沿う溝部に形成
されてなることを特徴とする回路基板。(4) The circuit board according to claim (1), wherein the conductive film is formed in a groove extending from the surface to the side surface of the stepped portion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59198466A JPS6177390A (en) | 1984-09-25 | 1984-09-25 | Circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59198466A JPS6177390A (en) | 1984-09-25 | 1984-09-25 | Circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6177390A true JPS6177390A (en) | 1986-04-19 |
Family
ID=16391573
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59198466A Pending JPS6177390A (en) | 1984-09-25 | 1984-09-25 | Circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6177390A (en) |
-
1984
- 1984-09-25 JP JP59198466A patent/JPS6177390A/en active Pending
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