JPS6177340A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To contrive to improve the reliability of the title device by preventing the separating of poly Si crystal into an Al wiring layer by a method wherein a silicide layer of high melting pint metal is adhered on a substrate by covering the contact region, and the wiring layer is formed after removal of the silicide layer in the part except the contact region. CONSTITUTION:A MOS transistor is formed in the element-forming region located by field oxide regions 2, and source-drain regions 3 and 4, a gate, an SiO2 layer 6, and PSG layer 7 are formed by normal proceses. As a barrier layer 8, the an MoSix layer of 150-300Angstrom thickness is adhered over the substrate by sputtering; next, the barrier layer 8 in the part except the contact window is etched away by a normal lithography process. Annealing is instantaneously carried out with a halogen lamp for 10 sec at 900 deg.C. As the wiring layer 9, an Al Si layer of 10,9000rho thickness is adhered over the substrate by evaporation, and the wiring layer 9 is patterned, resulting in the finish of element formation.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention is directed to the contact characteristics and reliability of a semiconductor device in which a barrier layer made of a silicide layer of a high melting point metal is interposed at the interface with a contact wiring layer in contact with a substrate. This invention relates to a manufacturing method for improving trajectory.

Pure aluminum (A
l) has been widely used. The reason for this is that it has a low specific resistance, has good adhesion to Si and silicon dioxide (Stow) Ji, and can form a good ohmic contact with a silicon (Si) substrate regardless of the conductivity type.

However, when pure At is used as the wiring layer, a eutectic alloy is formed at the interface where the metal oxide and the Si substrate contact each other due to low-temperature heat treatment during the process, resulting in deep etch pits in the Si substrate. In recent years, this has become a problem as semiconductor devices have become more highly integrated and the elements constituting the semiconductor devices have been miniaturized.

Therefore, an AlSi alloy has been used instead of AI as a wiring layer, but the Si epitaxial layer forms at the interface between the Al and the Si substrate due to heat treatment in the process or solid phase reaction even at lower temperatures. As it grew, it became the cause of poor contact.

In particular, as the contact window becomes smaller with miniaturization, the influence of the solid phase epitaxial layer becomes greater.

In order to prevent the growth of a solid phase epitaxial layer, a method in which a silicide layer of a high melting point metal is interposed as a barrier layer between an AI and a Si substrate has become frequently used.

The barrier layer includes molybdenum silicide (MoSix), tungsten silicide (WSi), titanium nitride (TiN), and the like.

However, when a barrier layer is interposed between the AI and Si substrates, for example in MoS i X, the state immediately after deposition is amorphous and the bond between Mo and Si is weak, so Si becomes free and enters the , poly-shaped Si crystals are precipitated.

^1 When poly-Si crystals precipitate in the wiring layer, the effective cross-sectional area of the wiring layer decreases, so the resistance of the wiring layer increases.
migration is likely to occur, significantly impeding reliability.

Therefore, a manufacturing method is desired that prevents a decrease in reliability due to precipitation of poly-S1 crystals in the At wiring layer of a semiconductor device in which a barrier layer is interposed between the AI and Si substrates.

[Conventional technology]

FIGS. 2A to 2C are cross-sectional views showing, in order of steps, a conventional method for manufacturing a semiconductor device having a barrier layer.

In FIG. 2(a), reference numeral 1 denotes a p-type St substrate, and a MOS is formed in the element formation region defined by the field oxidation region 2.
A transistor is formed. 3.4 is the n4 type source
Drain region, 5 is a gate made of polySt layer, 6 is S
The i01 layer and 7 represent phosphosilicate glass (PSG) layers, which are formed by normal steps up to this point.

Next, a barrier layer 8 is formed by sputtering to a thickness of 150~
A layer of 300 MoSix is deposited over the entire substrate.

Next, instantaneous annealing is carried out using a halogen lamp at 900 DEG C. for 10 seconds according to the method disclosed in Japanese Patent Application No. 159536/1982 by the present inventor.

By this instantaneous annealing, the A1 wiring layer can prevent the precipitation of Bo'JSi crystals to a large extent without deteriorating the contact characteristics.

In FIG. 2(b), an AlSi layer having a thickness of 10,000 wafers is deposited on the entire surface of the substrate as a layer 9 by vapor deposition.

In FIG. 2(e), the wiring layer 9 is patterned to complete the element formation.

[Problem that the invention seeks to solve]

Although the above-mentioned instantaneous annealing can considerably prevent the precipitation of poly-Si crystals, when Mos+ becomes more Si than X=2, the Si that does not participate in bonding still precipitates in the At wiring layer.

Since it is difficult to accurately control X in the production process, it has become necessary to take measures to suppress this Si precipitation.

[Means for solving problems]

The solution to the above problem is to provide a semiconductor device according to the present invention, in which a silicide layer of a refractory metal is deposited on a substrate to cover the contact area a, and after removing the silicide layer outside the contact area, a wiring layer is formed. This is achieved by a manufacturing method.

[Effect]

Since the barrier layer necessary for contact stabilization only needs to be within the contact window, the unnecessary barrier layer is removed by etching.

This causes excess St in the barrier layer to enter the At wiring layer.
decreases dramatically. Therefore, using the instantaneous annealing described above,
Precipitation of poly-Si crystals on the At wiring layer can be more completely prevented without deteriorating the contact characteristics of the At wiring layer to the St substrate.

〔Example〕

FIGS. 1A to 1C are cross-sectional views showing the method of manufacturing a semiconductor device having a barrier layer according to the present invention in order of steps.

In FIG. 1(a), reference numeral 1 denotes a p-type St substrate, in which a MOS is formed in an element formation region defined by a field oxidation region 2.
) a transistor is formed. Reference numerals 3 and 4 represent source/drain regions, 5 a gate, 6 a SiO□ layer, and 7 a PSG layer, which are formed by normal steps up to this point.

Next, a barrier layer 8 is formed by sputtering to a thickness of 150~
A layer of 300 MoSi is deposited over the entire substrate.

Next, the barrier layer 8 other than the contact window is etched and removed using a normal glue etching process.

Next, instantaneous annealing is performed using a halogen lamp at 900° C. for 10 seconds.

In the first issue), as the wiring layer 9, a 1000-thick ^ISi layer is deposited over the entire surface of the substrate by vapor deposition.

In FIG. 1(0), the wiring layer 9 is patterned to complete the element formation.

〔Effect of the invention〕

As explained in detail above, according to the present invention, the AI wiring layer and the Si substrate can be
Precipitation of polySt crystals into the wiring layer can be prevented, and therefore the reliability of the semiconductor device can be improved.

[Brief explanation of drawings]

FIGS. 1A to 1C are cross-sectional views showing the manufacturing method of a semiconductor device having a barrier layer according to the present invention in order of process, and FIGS. 2A to 2C are cross-sectional views of a semiconductor device having a barrier layer according to a conventional example. It is a sectional view showing the manufacturing method in the order of steps. In the figure, 1 is a p-type St substrate, 2 is a field oxidation region, 3.4 is a source/drain region, 5 is a gate, 6 is a SiO□ layer, and 7 is a PSG layer. ,
8 represents a barrier layer, and 9 represents a wiring layer. One nri-

Claims (1)

[Claims] 1. A method of manufacturing a semiconductor device, comprising depositing a silicide layer of a high melting point metal on a substrate to cover a contact region, and forming a wiring layer after removing the silicide layer other than the contact region.