JPS6056293B2 - Method for manufacturing semiconductor integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor circuit device having a structure in which a rib trimetal or an alloy of this metal and polysilicon is deposited between polysilicon and polysilicon.
The present invention relates to an OS type FET integrated circuit device.

In integrated circuit devices that integrate MOS type FETs, a silicon gate process is used because of the stability of the operation of the MOS type FETs and the fact that the gate electrode can be made self-aligned.

On the other hand, in order to increase the integration density and improve the performance of transistors, it is essential to shorten the channel length of transistors. As the channel length becomes shorter, it is necessary to reduce the depth Xj of the drain/source region, and therefore the concentration of the drain/source region decreases. Further, in a normal process in which high concentration impurities are simultaneously diffused into polysilicon used for wiring and gate electrodes and source/drain regions, the layer resistance of polysilicon becomes large. In addition to this problem, as polysilicon becomes smaller, the resistance of polysilicon increases. Such an increase in the resistance of polysilicon causes a decrease in circuit speed, and especially when polysilicon wiring is used as a row line (address bus) in a memory circuit, the decrease in the speed at which signals are transmitted through this row line reduces the operating margin. This has a large effect on the speed and speed of the circuit. On the other hand, in order to lower the resistance of polysilicon wiring, attempts have been made to deposit a metal called librag trimetal, such as PT, Mo, or W, on polysilicon. However, since such metals have sharp edges after etching, the Al interconnects running on these interconnects via an insulating film may be disconnected. Furthermore, in this wiring structure, polysilicon is oxidized like a normal silicon gate process, and this SiO. The method of using a film as the insulating film described above cannot be used. In order to compensate for these drawbacks, a phosphorus glass layer containing a high concentration of phosphorus is deposited on platinum or refractory metal by vapor phase growth, and the edges are made sloppy by heat treatment. However, the phosphine used in this vapor phase growth is extremely dangerous.
The vapor phase growth method using phosphorus glass is not suitable for mass production. In addition, in order to solve the above-mentioned problems, an integrated circuit device having a structure in which a metal called refractory metal such as Pt, MO, or W, or a composite metal of the metal and polysilicon is used at the bottom of polysilicon. There is an example.

However, if the above structure is used for the gate electrode, metals called refractory metals such as Pt, MO, and W will have a deep G.I. R, (GenerationOn-RecOmbi
rlaiOn) and cannot be used as a gate electrode because it causes leakage.

Therefore, it is necessary to perform a photoresist process to remove the gate portion. The present invention provides a semiconductor integrated circuit device with low resistance and no disconnection of metal wiring.

A method for manufacturing a semiconductor device according to the present invention includes the steps of forming a gate insulating film on a semiconductor substrate, forming a first polycrystalline silicon layer on the gate insulating film, and forming a first polycrystalline silicon layer on the first polycrystalline silicon layer. a step of forming a heat-resistant metal layer that alloys with silicon; a step of forming a second polycrystalline silicon layer on the metal layer; a step of selectively removing a multilayer structure of a polycrystalline silicon layer and a gate insulating film to leave at least a region matching the shape of the gate electrode; and the gate electrode.

Using the region of the multilayer structure left according to the shape as a mask, impurities are introduced into the semiconductor substrate and the second polycrystalline silicon and oxidized to form source and drain regions, and the second polycrystalline silicon is oxidized. Place a layer of phosphorus glass on top of the above sauce. The method is characterized by comprising the steps of forming an oxide film on the oxide film and the drain region, making the phosphorus glass layer loose by heat treatment, and forming a metal wiring layer on the oxide film. In the present invention, a semiconductor substrate on which source/drain regions are not formed is used as a starting material,
A multilayer structure consisting of a gate insulating film, a first polycrystalline silicon layer, a metal layer such as platinum, molybdenum, or tungsten, and a second polycrystalline silicon layer is formed on this, and this multilayer structure is selectively removed to form a gate electrode. Using the remaining multilayer structure as a mask, impurities are introduced and oxidized (heat treated) to form source and drain regions, and phosphorus glass is deposited on the topmost second polycrystalline silicon layer for the source and drain regions. An oxide film is created on top, and upper layer wiring is formed on this phosphorus glass and oxide film.

Therefore, self-alignment between the gate electrode and the source/drain regions is achieved. Further, in the present invention, the phosphorus glass on the second polycrystalline silicon layer is obtained by thermally oxidizing this second polycrystalline silicon layer, and
The edge of the polycrystalline silicon layer has a large roundness. Therefore, disconnection of the upper layer wiring formed thereon does not occur. The present invention will be explained by examples. FIG. 1 is a cross-sectional view of the manufacturing process of a semiconductor integrated circuit device according to a first embodiment of the present invention.

First, the Phillips ●Qusearch● report (Phlll
psResearchRepOrts) 1970, 2
Using an N-type semiconductor substrate 1 and gate insulating film 2 obtained by the LOCOS process as shown in Vol. 5, pages 118-132 as starting substrates, polysilicon is grown over the entire surface to form a polysilicon layer 3.

Further, Pt is deposited on the entire surface by sputtering to form a Pt layer 4, and a polysilicon layer 5 is grown on the entire surface.
Further, photoresist is applied to the entire surface, and photoresist 6 is selectively left in an area slightly larger than the area that will become the future wiring and gate electrode (FIG. 1a). Next, polysilicon layer 5 is selectively etched using photoresist 6 as a mask (FIG. 1b).

Next, the polysilicon layer 5 and the mask Pt layer 4 are selectively removed using aqua regia. (Figure 1c). Next, photoresist 6 and P
Polysilicon layer 3 and gate insulating film 2 are selectively etched using t-layer 4 as a mask.

At this time, the side surfaces of polysilicon layer 5 are also etched at the same time. (Figure 1d). Next, resource/drain regions 7 and 8 are formed by diffusing and oxidizing phosphorus.

At this time, a SiO2 film 9 having a phosphorus glass layer on its surface is formed. Furthermore, the Pt layer 4 is replaced by a PtSi layer 10 (FIG. 1e). Next, after a SiO2 film 11 is deposited by vapor phase growth, a contact hole is opened and an Al wiring 12 is formed, thereby obtaining a semiconductor integrated circuit device of the present invention (FIG. 1f). FIG. 2 is a cross-sectional view of the manufacturing process of a semiconductor integrated circuit device according to a second embodiment of the present invention.

A substrate having the same structure as that shown in FIG. 1d is manufactured using the same manufacturing method as in the first embodiment.

That is, a gate insulating film 22, a polysilicon layer 23, a Pt layer and a polysilicon layer 25 are formed on an N-type semiconductor substrate 21, and selectively etched in sequence in the same manner as in the first embodiment. (Figure 2a). Next, source/drain regions 27 and 28 are formed by diffusing and oxidizing phosphorus.

At this time, a SiO2 film 29 having a phosphorus glass layer on its surface is formed. Furthermore, the Pt layer 24 changes to a PtSi layer 30 (
Figure 2 b). Next, a contact hole is opened and an Al wiring 32 is formed, thereby completing the semiconductor integrated circuit device of the present invention.

(Figure 2c). As shown in the first and second embodiments above, there is a high concentration of phosphorus glass on the polysilicon in the wiring and gate parts, and it can be made loose by heat treatment, so disconnection of the A1 wiring can be avoided. Can be done.

The polysilicon/Pt or PtSi/polysilicon structure thus allows conventional silicon gate processes to be used as is. Although the above two embodiments have been described using Pt, other metals that can withstand high temperatures, such as MO and W, and alloys of these metals and polysilicon can also be used.

As described above in detail, according to the present invention, a silicon gate type semiconductor integrated circuit device with low resistance and no disconnection of wiring can be obtained, and its effects are remarkable.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a semiconductor integrated circuit device according to a first embodiment of the present invention in a manufacturing process, and FIG. 2 is a cross-sectional view of a semiconductor integrated circuit device according to a second embodiment of the present invention in a manufacturing process. 1, 21... N-type semiconductor substrate, 2, 22...
...gate insulating film, 3,23...polysilicon layer,
4,24...Pt layer, 5,25...polysilicon layer, 6...photoresist, 7,27...
Source region, 8, 28...Drain region, 9,
29...SiO2 film, 10,30...P
tSi layer, 11... SiO2 film, 12, 32...
...N wiring.

Claims (1)

[Claims] 1. A step of forming a gate insulating film on a semiconductor substrate, a step of forming a first polycrystalline silicon layer on the gate insulating film, and a step of forming a heat-resistant metal to be alloyed with silicon on the first polycrystalline silicon layer. a step of forming a second polycrystalline silicon layer on the metal layer, the second polycrystalline silicon layer, the metal layer, the first polycrystalline silicon layer and a gate insulating film. a step of selectively removing the multilayer structure to leave at least a region matching the shape of the gate electrode; and a step of removing impurities from the semiconductor substrate and the second layer using the region of the multilayer structure left matching the shape of the gate electrode as a mask. introducing into polycrystalline silicon and oxidizing it to form source and drain regions, forming a phosphorus glass layer on the second polycrystalline silicon layer and forming an oxide film on the source and drain regions; A method for manufacturing a semiconductor integrated circuit device, comprising the steps of: sagging by heat treatment; and forming a metal wiring layer on the oxide film.