JP2534269B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor device having a conductive layer having a polycide structure.

[Conventional technology]

In recent years, as semiconductor devices have become highly integrated and miniaturized,
In the past, various problems that did not pose a problem have come to the surface as problems, and new manufacturing processes have been actively developed and improved to improve them. The thermal problem in the manufacturing process is one of the important issues, and in the future, it is necessary to lower the process temperature.

FIG. 3 shows a conventional method for manufacturing a semiconductor device.
9A to 9E are cross-sectional views sequentially showing the manufacturing process of the transistor portion.

In the figure, (1) is a P conductivity type (hereinafter referred to as P type).
Regarding the N conductivity type, hereinafter, it will be referred to as N type) semiconductor substrate (hereinafter referred to as substrate), and (2) will be referred to as this substrate (1).
A thin silicon oxide film formed on one main surface of the thin silicon oxide film that can serve as a gate oxide film (2a), (3) is a two-layer gate electrode formed on this thin silicon oxide film (2), and (4) is this The first polycrystalline silicon layer forming the lower layer portion of the gate electrode (3), (5) forming the upper layer portion of the gate electrode (3), molybdenum silicide (MoSi ₂ ), tungsten silicide (WSi ₂ ), etc. The refractory metal silicide layer (hereinafter, referred to as a silicide layer) (6) is made by ion implantation with ions such as phosphorus and arsenic. (7) is an N-type impurity layer formed by performing the ion implantation (6) on one main surface of the substrate (1), and is a source region (8) of the N-type diffusion layer.
a) and the drain region (8b). (9) is an insulating layer for interlayer insulation formed of a silicon oxide film on one main surface of the substrate (1), and (10) is formed on the upper surface of the insulating layer (9) and has a flat interlayer insulating layer. Boron / phosphorus / silicate glass (hereinafter referred to as BPSG), which is a reflowable material, (11) is a silicon oxide layer formed on one main surface of the silicide layer (5) in the gate electrode (3).

The semiconductor device configured as described above is obtained through the following manufacturing process. First, a thin silicon oxide film (2) is formed on one main surface of a substrate (1) by a thermal oxidation method or the like, and further, a first polycrystalline silicon layer (4) has a thickness of about 3000 Å.
Is formed by a CVD method or the like to have a low resistance by a phosphorus treatment or the like, and then a silicide layer (5), for example, a tungsten silicide layer is formed by a sputtering method or the like to a thickness of about 2300Å (see FIG. 3). (A)).

Next, the silicide layer (5) and the first polycrystalline silicon layer (4) are patterned by a photolithography process to form a two-layer gate electrode (3) having a polycide structure (third). Figure (b)).

Next, ion implantation (6) of, for example, arsenic ions is performed from one main surface side of the substrate (1) under predetermined implantation conditions,
The gate electrode (3) portion serves as a mask, and N-type impurity layers (7) are formed in predetermined regions on one main surface of the substrate (1) on both sides of the mask (FIG. 3 (c)). After that, heat treatment is performed, for example, at about 900 ° C. for 60 minutes to form the N-type impurity layer (7) as an N-type diffusion layer and form a source region (8a) and a drain region (8b). A channel portion is formed between the source region (8a) and the drain region (8b), and the gate electrode (3) is formed via the source region (8a), the drain region (8b) and the gate oxide film (2a). And form a MOS transistor. By the heat treatment, a thin oxide layer (not shown) is formed on the one main surface of the metal silicide (5).

Next, an insulating layer (9) is formed on one main surface of the substrate (1).
After being formed to a thickness of 2000Å by the CVD method, etc., further BPSG (1
0) is formed to a thickness of about 8000Å by the CVD method (3rd
Figure (d)).

Next, the BPSG (10) is subjected to reflow oxidation for 30 minutes in a wet atmosphere at, for example, about 900 ° C. to be a flattened BPSG (10a). By this reflow oxidation, a silicon oxide film (11) is formed on one main surface of the silicide layer (5), and the gate electrode (3) is mainly formed on the main surface in the process of forming the silicon oxide film (11). The center portion of the surface is concavely curved (Fig. 3 (e)).

After that, a contact hole is formed in the flattened BPSG (10a) and the insulating layer (9) by patterning by a photolithography process, and then a wiring material such as aluminum is formed on the entire surface. The gate electrode (3), the source region (8a), and the drain region (8b) are formed on the flattened BPSG (10a) which has been patterned by a lithography process, through contact holes.
Etc., an aluminum wiring layer and the like connected to the above are formed.

As described above, the heat treatment after the ion implantation (6) recovers damage to the impurity layer implanted with predetermined ions,
The heat treatment in the reflow oxidation flattens the BPSG (10) to reduce the step difference, and prevents the disconnection during the formation of the aluminum wiring layer, etc. The above heat treatment is an essential step in manufacturing.

[Problems to be solved by the invention]

Since the conventional method for manufacturing a semiconductor device is configured as described above, the gate electrode (3) is affected by the oxidation reaction due to the heat treatment after ion implantation or the heat treatment in the reflow oxidation. That is, the former heat treatment produces a thin oxide layer on one main surface of the gate electrode (3), that is, one main surface of the silicide layer (5), and the silicide of the silicide layer (5) is crystallized. To be done. When the silicide layer (5) is made of, for example, tungsten silicide, the generated oxide layer is made of an oxide with a silicide such as tungsten dioxide (WO ₂ ) or tungsten trioxide (WO ₃ ) or a silicon oxide film. In this case, the silicide layer (5) faces the heat treatment space and is in an oxygen-rich (sich) state, while the first polycrystalline silicon layer (4) serving as a silicon source is located below the silicide layer (5). Therefore, the generation of the silicon oxide film is controlled by the amount of silicon supplied by thermal diffusion in the silicide layer (5). Since the produced oxide layer has a porous structural characteristic, it can easily diffuse oxygen and silicon that contribute to the formation of the oxide layer. Further, when the silicide layer (5) exceeds a predetermined temperature. Since the silicide begins to crystallize and the crystal grain size is gradually increased, the crystal grain boundary is also enlarged and the silicon which is directed toward the upper side from the first polycrystalline silicon layer (4) on the lower side is easily diffused. It can be done.

When the oxide layer is formed on one main surface of the gate electrode (3) through such a process, electrical characteristics such as an increase in sheet resistance of the gate and an increase in contact resistance when connecting with another wiring layer are obtained. Will cause the problem of.

The gate electrode (3) is formed by the latter heat treatment.
The silicon oxide film (11) is actively formed on one main surface of the. This is because silicon from the first polycrystalline silicon layer (4) thermally diffuses in the silicide layer (5) toward the upper layer side, and oxygen from the heat treatment space and the gate electrode (3). When they are thermally diffused in the BPSG (10) and the insulating layer (9) toward the side and reach the one main surface of the silicide layer (5), they are bonded there and the silicon oxide film (11) is formed. ) Is generated. In this case, the silicide layer (5) is in a silicon-rich state in which silicon is sufficiently supplied from the first polycrystalline silicon layer (4) on the lower side thereof, while the silicide layer (5) is one of the silicide layers (5). The insulation layer (9) and BPSG (10) on the main surface
Therefore, the formation of the silicon oxide film (11) is limited by the amount of oxygen supplied by thermal diffusion in the BPSG (10) and the insulating layer (9).

Such a silicon oxide film (11) gradually grows with the lapse of time of reflow oxidation to increase its film thickness, and conversely, silicon decreases from the first polycrystalline silicon layer (4). Go on. At the end of the reflow oxidation, as shown in FIG. 3 (e), the gate electrode (3) has a concave shape in the central portion of one main surface thereof, and in some cases, the silicide layer (5). ), The shape of the first polycrystalline silicon layer (4) is deteriorated such as peeling at the bonding interface. Therefore, the transistor characteristics are deteriorated, such as non-uniformity of the threshold voltage and reduction of the gate breakdown voltage. As described above, there is a problem that any of the above heat treatments leads to deterioration of electrical characteristics, resulting in impaired reliability.

The present invention has been made to solve the above problems, the conductive layer is protected to a normal shape,
An object of the present invention is to obtain a highly reliable method for manufacturing a semiconductor device having excellent electric characteristics.

[Means for solving problems]

In the method for manufacturing a semiconductor device according to the present invention, a conductive layer including a first polycrystalline silicon layer and a silicide layer is formed on a semiconductor substrate, and the first polycrystalline silicon layer is protected on the conductive layer. A second polycrystalline silicon layer is formed to form a gate electrode, and an insulating layer is used to perform interlayer insulation of each layer forming the gate electrode, and a sidewall portion of the gate electrode is formed at the time of reflow oxidation of the insulating layer. The second polycrystalline silicon layer is partially oxidized with almost no oxidation.

[Action]

The second polycrystalline silicon layer in the present invention is placed on the conductive layer and effectively reacts with the thermal diffusion component while maintaining a stable state with the conductive layer. This prevents the silicon in the silicon layer from reacting with the thermal diffusion component, and suppresses the oxidation of the side wall of the gate electrode.

Example of Invention

An embodiment of the present invention will be described below with reference to the drawings. Note that the description of the part overlapping with the description of the conventional technique will be omitted as appropriate. FIG. 1 is a sectional view showing an embodiment of the present invention, and FIGS. 1 (a) to (e) are views sequentially showing the manufacturing process of the transistor portion thereof. The structure shown in FIG. 1 differs from that shown in FIG. 3 in the following points. That is, in the figure, (1) (2) and (4) to (10)
Is the same as the conventional one, (12) is a gate electrode to be a conductive layer, (13) is a second polycrystalline silicon layer, and (14) is a silicon oxide film. The gate electrode (12) is composed of the first polycrystalline silicon layer (4) and molybdenum silicide (MOS).
i ₂ ), a silicide layer (5) made of tungsten silicide (WBi ₂ ), etc. and a polycide structure in a two-layer structure, and a second polycrystalline silicon layer (13) is formed on one main surface thereof. In this structure, the upper layer can be converted into a silicon oxide film (14) by a reaction.

The semiconductor device configured as described above is obtained through the following manufacturing process. First, a thin silicon oxide film (2) that can be a gate oxide film (2a) is formed on one main surface of a P-type substrate (1) by a thermal oxidation method or the like, and then a first polycrystalline silicon layer (4) is formed. Is formed to a thickness of about 3000 Å by the CVD method, etc., and is made to have a low resistance by phosphorus treatment or the like, and then a silicide layer (5), for example, tungsten silicide (WSi ₂ )
A layer is formed to a thickness of about 2300Å by a sputtering method or the like, and a second polycrystalline silicon layer (13) is formed to a thickness of about 500Å by a CVD method or the like (Fig. 1 (a)).

Next, the second polycrystalline silicon layer (13), the silicide layer (5) and the first polycrystalline silicon layer (4) are patterned by a photolithography process, and the second polycrystalline silicon is formed on the upper layer. A gate electrode (12) having a layer (13) is formed (FIG. 1 (b)).

Next, ion implantation (6) of, for example, arsenic ions is performed from one main surface side of the substrate (1) under predetermined implantation conditions,
The gate electrode (12) portion serves as a mask, and N-type impurity layers (7) are formed in the regions of the one main surface of the substrate (1) on both sides thereof (FIG. 1 (c)). After that, heat treatment is performed, for example, at about 900 ° C. for 60 minutes to form the N-type impurity layer (7) as an N-type diffusion layer and form a source region (8a) and a drain region (8b). A channel portion is formed between the source region (8a) and the drain region (8b) on one main surface of the substrate (1), and the source region (8a), the drain region (8b) and the gate oxide film (2a) are interposed therebetween. With the gate electrode (12) thus formed, a MOS transistor is formed.

Then, an insulating layer (9) made of a silicon oxide film is formed on the entire main surface of the substrate (1) so as to cover the gate electrode (12) by a CVD method or the like to a thickness of about 2000Å. , Reflow material for planarization of interlayer insulation layer, eg BP
SG (10) is formed to a thickness of about 8000Å by the CVD method or the like (Fig. 1 (d)).

Next, the BPSG (10) is flattened by performing reflow oxidation for 30 minutes in a Wet atmosphere at about 900 ° C.
a) (Fig. 1 (e)). After that, a patterning process is performed by a photolithography process to form a contact hole (not shown) in a predetermined portion of the flattened BPSG (10a) and insulating layer (9). The gate electrode (12), the source region (8a), and the drain region (8b) are formed through contact holes on the BPSG (10a) that is flattened by forming a aluminum film and performing a patterning process by a photolithography process.
An upper layer wiring (not shown) made of aluminum wiring connected to one main surface of the above is formed. The upper layer wiring is, for example, a wiring corresponding to the bit line of the memory device. The formation of the BPSG (10) and its reflow oxidation treatment are performed prior to the formation of the upper wiring by the gate electrode (1
By reducing the steep step in the insulating layer (9) caused by the section 2) by flattening the BPSG (10), disconnection in the step portion of the upper layer wiring can be prevented and highly accurate processing can be performed. It is a squeal.

Thus, according to the above embodiment, the gate electrode (12)
Has a second polycrystalline silicon layer (13) which maintains a stable state on one main surface of the gate electrode (12), and one main surface of the gate electrode (12) is directly contacted with the heat treatment after the ion implantation (6). The protection can be achieved without being exposed to the heat treatment space. Further, also in the heat treatment of the reflow oxidation, the gate electrode (12) can be similarly protected. That is, in the case of the former heat treatment, oxygen from the heat treatment space first reacts with the silicon of the second polycrystalline silicon layer (13), and in the case of the latter heat treatment,
Oxygen which thermally diffuses in the insulating layer (9) and BPSG (10) toward the gate electrode (12) side first reacts with the silicon of the second polycrystalline silicon layer (13). Then, due to these reactions, the second polycrystalline silicon layer (13) changes from its upper layer portion to the silicon oxide film (14). In the case of the heat treatment above, this reaction is
The second polycrystalline silicon layer (13) is left in an amount of about 100 to 200Å. Thus, the reaction is
2) The second polycrystalline silicon layer (13) above the upper layer
Will be performed only between the gate electrode (1
2) It does not reach the first polycrystalline silicon layer (4) forming the lower layer portion. In addition, one main surface of the silicide layer (5) forming the upper layer portion of the gate electrode (12) has the above-mentioned second surface.
Since it is joined to the polycrystalline silicon layer (13) and oxygen does not diffuse, an oxide with silicide is not generated and the side wall of the gate electrode is hardly oxidized. Therefore, the upper layer wiring is directly joined to the silicide layer (5) and desired characteristics are obtained. As described above, the gate electrode (12) is protected without being affected by the oxidation reaction in the heat treatment, and the shape of the gate electrode (12) can be normally maintained to obtain the desired one. A transistor having characteristics will be formed.

FIG. 2 is a sectional view showing another embodiment of the present invention.
(A) to (g) are the LDD (Lightly Doped Drain)
It is a figure which shows the manufacturing process of the transistor part of a structure. Second
The configuration shown in the figure differs from that shown in FIG. 3 in the following points. That is, in the figure, (1
5) is a first N-type impurity layer, (16) is a sidewall made of a silicon oxide film, (17) is a second N-type impurity layer,
(18a) and (18b) are a source region and a drain region. This has a second polycrystalline silicon layer (13) on the gate electrode (12), and the gate electrode (12)
A side wall (16) is formed on the step portion with the thin silicon oxide film (2) on the side wall side of. On both sides of the channel portion on one main surface of the substrate (1), the shallow junction to the bottom portion of the side wall (16) N ^- has an area (15a) (15b), further the N to the outer region ^- Area (15a) (15b)
Higher concentration, deeper junctions of N ⁺ regions (17a) (17b) exist, and these N ⁻ regions (15a) (15b) and N ⁺ regions (17a) (17a) (17a) (17b)
b) a source region (18a) and a drain region (18a)
b) is formed.

By the way, the semiconductor device configured as described above is obtained through the following manufacturing steps. That is, first, P
A thin silicon oxide film (2), which can be a gate oxide film (2a), is formed on one main surface of the shaped substrate (1) by a thermal oxidation method or the like, and then a first polycrystalline silicon layer (4) of about 3000 Å is formed. Is formed by a CVD method or the like to have a low resistance by phosphorus treatment or the like, and then a silicide layer (5), for example, a tungsten silicide (WSi ₂ ) layer is formed to a thickness of about 2300 Å by a sputtering method or the like. Furthermore, the second polycrystalline silicon layer (1
3) is formed by a CVD method or the like to a thickness of about 500Å (second
Figure (a)).

Next, the second polycrystalline silicon layer (13), the silicide layer (5) and the first polycrystalline silicon layer (4) are patterned by a photolithography process, and the second polycrystalline silicon is formed on the upper layer. A two-layer gate electrode (12) having a polycide structure having a layer (13) is formed (FIG. 2 (b)).

Next, ion implantation (6) of, for example, arsenic ions is performed from one main surface side of the substrate (1) under predetermined implantation conditions,
The gate electrode (12) portion serves as a mask to form the first N-type impurity layer (15) having a shallow junction on both sides of the channel portion of the substrate (1) (FIG. 2 (c)). Then, heat treatment is performed so that the first N-type impurity layer (15) has a source region (18a) and a drain region (18).
b) is a part of N ^- region (15a) (15b).

Next, a silicon oxide film which will be a part of an insulating layer is formed on the entire main surface of the substrate (1) to a thickness of about 2500 Å by a CVD method or the like, and then reactive ion etching (hereinafter referred to as RIE).
Method) is used to etch the entire surface of the silicon oxide film. After RIE, the gate electrode (1
2), the silicon oxide film remains only on the step portion on the side surface side of the second polycrystalline silicon layer (13), and the side wall (16) made of the silicon oxide film is formed (FIG. 2 (d)). ). The bottom of this side wall (16) is about 2500
Å It becomes a weak size.

Next, from the one main surface side of the substrate (1), ion implantation (6) of, for example, arsenic ions is performed under the implantation conditions of higher concentration and deeper junction than the first N-type impurity layer (15). The gate electrode (12) and side wall (16)
Is used as a mask to form a second N-type impurity layer (17) on the main surface of the substrate (1) outside the sidewall (16) (FIG. 2 (e)). After this, heat treatment is performed, for example, at about 900 ° C. for 60 minutes, and the second N
The type impurity layer (17) is formed as an N type diffusion layer, and the N ⁺ region (17
a) (17b) is formed. Therefore, the channel portion is sandwiched on one main surface of the substrate (1) and the N ^- regions (15a) (15b)
And the N ⁺ region (17a) (17b) and the source region (18
a), the drain region (18b) is formed.

Next, an insulating layer (9) made of a silicon oxide film is formed on the entire main surface of the substrate (1) by a CVD method or the like to a thickness of about 2000 Å, and a reflow process for flattening the interlayer insulating layer is performed. A material, for example, BPSG (10) is formed by the CVD method or the like to a thickness of about 8000Å (Fig. 2 (f)).

Next, the BPSG (10) is flattened by performing reflow oxidation for 30 minutes in a Wet atmosphere at about 900 ° C.
a) (Fig. 2 (g)). After that, the above-mentioned flattened BPSG (10
a) Upper layer wiring will be formed on top.

Also in the above-mentioned other embodiment configured in this way,
A second polycrystalline silicon layer (1
Since it has 3), in the heat treatment after the ion implantation (6) or the heat treatment in the reflow oxidation, oxygen directly reaching from the heat treatment space, BPSG (10), insulating layer (9)
Oxygen that thermally diffuses inside the chamber toward the gate electrode (12) first reaches the second polycrystalline silicon layer (13), is bonded to the silicon, and gradually becomes a silicon oxide film (14) from the upper layer portion. Will change to.

Then, in the heat treatment, as long as the second polycrystalline silicon layer (13) is present, only the reaction in this region proceeds, and in this case, the second polycrystalline silicon layer (13) is About 100 to 200 Å remains, and the upper layer part reacts with oxygen to change and become a grown silicon oxide film (14). Therefore, in this case, the oxygen is not further thermally diffused to the gate electrode (12) side, and the oxygen does not react with the first polycrystalline silicon layer (4) in the gate electrode (12). In addition, the reaction of oxide formation with the silicide in the metal silicide layer (5) does not occur similarly. Therefore, the gate electrode (12) is protected without being affected by the above oxidation reaction.

Further, the second polycrystalline silicon layer (13) is formed on the gate electrode (1) during the RIE for forming the sidewall (16).
2) In particular, one main surface of the silicide layer (5) is exposed, and it also has a function of suppressing exposure to the etching space and reaction with the gas.

As described above, according to the embodiment of the present invention, since the silicon of the first polycrystalline silicon layer (4) in the gate electrode (12) is inhibited from reacting with oxygen produced by the heat treatment, The gate electrode (12) is to be normally connected to the wiring and the like, and the silicon in the first polycrystalline silicon layer (4) is reduced so that the main part of the gate electrode (12) is reduced. Curvature in the surface is also prevented.

Therefore, the gate electrode (12) can be formed in a normal shape and have excellent electric characteristics.

In the description of each of the above embodiments, the element structure is P
Although the case where the N-type diffusion layer is formed on the shaped substrate (1) and the MOS transistor is formed is shown, the present invention is not limited to this, and the substrate (1) and the diffusion layer may have the opposite conductivity type. Of course, the element structure to be formed may be another element structure such as a BIP transistor.

Further, the second polycrystalline silicon layer (13) provided on the conductive layer may be either doped polycrystalline silicon or non-doped polycrystalline silicon, and its structure is initially about 500Å thick. The case where the upper layer portion is changed to the silicon oxide film (14) after being formed by reflow oxidation and leaving about 100 to 200 Å is shown, but the present invention is not limited to this, and the second polycrystalline silicon layer (13)
Has an effect if it remains slightly after the reflow oxidation, and the thickness of the second polycrystalline silicon layer (13) and the thicknesses of other layers can be increased depending on the heat treatment conditions such as the reflow oxidation. The same effects as described above can be obtained even when the above-mentioned materials are appropriately selected and formed.

〔The invention's effect〕

As described above, according to the present invention, the second polycrystalline silicon layer is provided on the conductive layer composed of the first polycrystalline silicon layer and the silicide layer to protect the first polycrystalline silicon layer. As a result, a conductive layer having a normal shape can be obtained, and excellent electrical characteristics and high reliability can be obtained.

BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1 (a) to (e) are sectional views of a manufacturing process of a transistor section showing a method of manufacturing a semiconductor device according to an embodiment of the present invention, and FIGS. 2 (a) to (g). 3A to 3E are sectional views of a transistor section showing a method of manufacturing a semiconductor device according to another embodiment of the present invention. FIGS. 3A to 3E are manufacturing steps of a transistor section showing a conventional method of manufacturing a semiconductor device. FIG. In the figure, (1) is a semiconductor substrate, (4) is a first polycrystalline silicon layer, (5) is a silicide layer, (9) is an insulating layer, (10) is BPSG, (12) is a gate electrode, ( 13) is the second
Is a polycrystalline silicon layer. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

(57) [Claims] 1. A first substrate on a semiconductor substrate with a gate insulating film interposed therebetween.
A first step of forming a polycrystalline silicon layer, a second step of forming a refractory metal silicide layer on the first polycrystalline silicon layer, and a second polycrystalline silicon on the refractory metal silicide layer Third step of forming a layer, patterning the first polycrystalline silicon layer, refractory metal silicide layer and second polycrystalline silicon layer to form a gate electrode on the semiconductor substrate The fifth step of implanting impurities into the one main surface of the semiconductor substrate,
A sixth step of heat-treating and diffusing the impurities implanted into the one main surface of the semiconductor substrate, and CVD so as to cover at least the first polycrystalline silicon layer and the refractory metal silicide layer.
The seventh step of forming an insulating film by a method such as a thermal oxidation process, the surface of the insulating film is flattened by thermal oxidation, and the sidewall of the gate electrode is not oxidized.
8. A method of manufacturing a semiconductor device, comprising an eighth step of oxidizing a part of the polycrystalline silicon layer.