JPS6173388A - Semiconductor light-emitting element - Google Patents

Semiconductor light-emitting element

Info

Publication number
JPS6173388A
JPS6173388A JP59193960A JP19396084A JPS6173388A JP S6173388 A JPS6173388 A JP S6173388A JP 59193960 A JP59193960 A JP 59193960A JP 19396084 A JP19396084 A JP 19396084A JP S6173388 A JPS6173388 A JP S6173388A
Authority
JP
Japan
Prior art keywords
layer
type
gaalas
light
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59193960A
Other languages
Japanese (ja)
Inventor
Tadashi Komatsubara
小松原 正
Tetsuo Sadamasa
定政 哲雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP59193960A priority Critical patent/JPS6173388A/en
Publication of JPS6173388A publication Critical patent/JPS6173388A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/0004Devices characterised by their operation
    • H01L33/002Devices characterised by their operation having heterojunctions or graded gap
    • H01L33/0025Devices characterised by their operation having heterojunctions or graded gap comprising only AIIIBV compounds

Abstract

PURPOSE:To give even an optical extracting window an effective electrode function, to increase longitudinal currents in currents flowing through a light- emitting layer consisting of a double hetero-junction and to improve luminous efficiency by forming a GaAlAs layer having low resistance and low Al concentration onto the light-emitting layer and using the GaAlAs layer as the optical extracting window. CONSTITUTION:An n-type GaAs layer 22 as a current constriction layer is deposited on a p-type GaAs substrate 21, a p-type GaAs layer 23 is diffused and formed at the central section of the layer 22, and a p-type GaAlAs clad layer 24 constituting a light-emitting layer consisting of a double hetero-junction, a p-type GaAlAs active layer 25, and an n-type GaAlAs clad layer 26 are laminated and grown on the whole surface containing the layer 23. An n-type GaAlAs layer 27, the composition ratio of Al therein is approximately twice as large as the active layer 25 and impurity concentration thereof extends over 1X10<18>/cm<3> or more, is deposited onto the layer 26, an n<+> type GaAs cap layer 28 and an electrode 29 are shaped onto the layer 27, and an optical extracting window 31 is bored to expose one part of the layer 27. An electrode 30 is also provided onto the back of the substrate 21.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は、ダブルへテロ接合を持つ面発光型の半導体発
光素子に関する。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a surface-emitting type semiconductor light emitting device having a double heterojunction.

〔発明の技術的背景とその問題点〕[Technical background of the invention and its problems]

GaAgAs /GaAs のダブルへテロ接合型光光
素子はこれまで数多く発弄されている。中でも発光素子
内を流れる電流路を絞ることによって点光源で高′f4
度の得られる発光素子の開発が盛んである。
Many GaAgAs/GaAs double heterojunction optical devices have been developed so far. In particular, by narrowing down the current path flowing inside the light emitting element, high f4 can be achieved with a point light source.
The development of light-emitting devices that provide high performance is active.

例えば第2図のような発光素子が発表されている( I
EEE Transactions On Compo
nents Hybrid AndManufactu
aring Technology : Vol 、 
CHMT−3、No、 4 Dec、  198(J)
 。11はp型GaAs基板であり、この上(=電流狭
窄層となるn型GaAs層12が選択的(皿形成されて
いる。このような基体上にp型Ga7v!Asクラッド
In 13 、 p 12 GaAj!Aa活i生fs
H4,n型GaAAAsクラッド層15を1臓次積層し
たダブルへテロ接合からなる発光j−が形成されている
。n型Qa IJ Asクラッドfg415の表面には
オーミックコンタクトを良好にするためのn型GaAs
キャップ層16を弁じて第1の電極17が形成され、基
板11裏面には第2の板極18が形成されている。光取
出し部となるクラッド層15の上はキャップ層が取り除
かれ、ここに鼠化シリコン腺からなる光取出し窓19が
形成されている。値化シリコン膜はGaAlAsよりも
屈折率が小さく、従って効率よく発光層からの光を取出
すことができる。
For example, a light emitting device as shown in Figure 2 has been announced (I
EEE Transactions On Compo
nents Hybrid And Manufacture
Aring Technology: Vol.
CHMT-3, No. 4 Dec, 198(J)
. 11 is a p-type GaAs substrate, on which an n-type GaAs layer 12 (=current confinement layer) is selectively formed. GaAj!Aa life fs
A light emitting j- is formed by a double heterojunction in which an H4, n-type GaAAAs cladding layer 15 is laminated one by one. The surface of the n-type Qa IJ As clad fg415 is coated with n-type GaAs for good ohmic contact.
A first electrode 17 is formed on the cap layer 16, and a second plate electrode 18 is formed on the back surface of the substrate 11. The cap layer is removed from above the cladding layer 15, which serves as a light extraction portion, and a light extraction window 19 made of a mouse silicon gland is formed there. The value-added silicon film has a refractive index lower than that of GaAlAs, and therefore can efficiently extract light from the light emitting layer.

ところがこの様な面発光型の発光素子には、次のような
問題がある。高輝度の点光源発光素子を得るためには、
素子の電流路を十分に絞シ込むこと、即ち、光取出し窓
19の径(ニルべて一流狭窄層12により紋る電流通路
を十分(=小さくすることが必要である。この場合、発
光層をtM、れる電流は、クラッド層15 、活性層1
4.クラッド層13を斜めに横切って流れること(=な
る。従って電流路が長くなり、直列抵抗が大きくなって
、発光素子の動作心圧が高くなる。これにより無用な′
磁力消費が瑠え、実効的な発光効率が低くなる。
However, such surface emitting type light emitting elements have the following problems. In order to obtain a high brightness point source light emitting device,
It is necessary to sufficiently constrict the current path of the element, that is, to make the diameter of the light extraction window 19 sufficiently small (= the diameter of the light extraction window 19) and the current path formed by the first confinement layer 12. tM, the current flowing through the cladding layer 15 and the active layer 1 is
4. The current flow diagonally across the cladding layer 13 (=). Therefore, the current path becomes longer, the series resistance becomes larger, and the operating heart pressure of the light emitting element becomes higher.
Magnetic power consumption increases and effective luminous efficiency decreases.

〔発明の目的〕[Purpose of the invention]

本発明は上吊の点(=鑑みなされたもので、電流路を短
くして動作4圧を低くし、もって高輝度の点光源を実現
した面発光型の半導体発光素子を提供することを目的と
する。
The present invention was made in consideration of the above-mentioned problem, and an object of the present invention is to provide a surface-emitting type semiconductor light-emitting device that shortens the current path, lowers the operating voltage, and thereby realizes a high-intensity point light source. do.

〔発明の概要〕[Summary of the invention]

本発明に、ダブルへテロ接合からなる発光層の上(=低
抵抗(l x IQ17cm3以下)でuaaro低い
GaAlAs層を形成し、そのGaAlAs層を光取り
出し窓として用いるようにしたことを特徴とする。
The present invention is characterized in that a GaAlAs layer with low resistance (l x IQ 17 cm3 or less) and low uaaro is formed on the light emitting layer consisting of a double heterojunction, and the GaAlAs layer is used as a light extraction window. .

〔発明の効果〕〔Effect of the invention〕

本発−!At二よれば、光取出し窓(GaAlAs層)
s実効的な電極として働き、従って発光j―を流れる一
流が従来のように糾め方間のみでなく坂万回にも多く流
れる結果、実効的に礒威路が短くなる。即ち素子の直列
抵抗が小さくな9、−作磁圧が低くて衝み、無駄な磁力
消費がなくなるため、発光効率の制い高輝度の点元隠を
得ることかでさる。また光取出し窓をGaAs盾で形成
するよりも光吸収が少なく実効的な発光効率を低下させ
ることもほとんどない。さらに元取出し窓として用いる
GaAlAs層はGaAsf曽(キャツフ゛層)のエツ
チング時のストッパーとして利用でさる為、装a工程に
おける利点ともなる。
Main departure! According to At2, the light extraction window (GaAlAs layer)
s acts as an effective electrode, and therefore the current flowing through the light emitting j- flows not only in the conventional way but also in the slope, effectively shortening the power path. That is, since the series resistance of the element is small, the magnetic actuation pressure is low and there is no unnecessary consumption of magnetic force, thereby controlling the luminous efficiency and obtaining a high brightness point source. In addition, the light absorption is smaller than when the light extraction window is formed of a GaAs shield, and there is almost no reduction in the effective luminous efficiency. Furthermore, since the GaAlAs layer used as the original extraction window can be used as a stopper during etching of the GaAsf layer (catch layer), it is also advantageous in the mounting process.

〔発明の実施列」 以下奄発明の詳細な説明する。第1図は、実施例の素子
傳造を示す。21はp型GaAs基板でろす、この上に
覗流狭窄層となるn fJI GaAs 1822が形
成され、その一部に例えばZn拡散(=よって電流通路
となるp型GaAs層るが形成されている。この基体の
上(=、ダブルへテロ接合を構成する発光層として、p
型GaAlAsクラッド+I24.p型GaAA!As
活性層5゜n型GaAj!Asクラッド1ii26が順
次積層されている。
[Sequence of implementation of the invention] A detailed explanation of the invention will be given below. FIG. 1 shows the construction of an example element. 21 is a p-type GaAs substrate, on which a p-type GaAs 1822 layer that becomes a peek current constriction layer is formed, and a part of it is formed with, for example, Zn diffusion (=therefore, a p-type GaAs layer that becomes a current path). On this substrate (=, as a light emitting layer constituting a double heterojunction,
Type GaAlAs clad + I24. p-type GaAA! As
Active layer 5゜n-type GaAj! As cladding 1ii26 is sequentially laminated.

両クラッド層24.26のk1m成比は活性層5の約6
〜10倍とする。この発光層の上(−はn型GaAlA
s層ゴとn+型GaAsキャップ層あを介して第1の1
4.&四が形成され、光取り出し部はこのn m Ga
AlAs @2’1と同じn型GaA7Asの薄膜から
なる光取出し窓31がル成されている。このn型GaA
lAs @27のA1組成比は活性層の約2倍でGa 
l−X AIX A3と表わした時、Xが0.15以下
で、またその不純物濃度はI X 10”/Cm3以上
である。なお基板21の裏面には第2の電極力が形成さ
れている。
The k1m ratio of both cladding layers 24.26 is about 6 of that of the active layer 5.
~10 times. Above this light emitting layer (- is n-type GaAlA
The first layer is formed through the s layer and the n+ type GaAs cap layer
4. &4 is formed, and the light extraction part is this nm Ga
A light extraction window 31 made of the same n-type GaA7As thin film as AlAs@2'1 is formed. This n-type GaA
The A1 composition ratio of lAs@27 is about twice that of the active layer, and Ga
When expressed as l-X AIX A3, X is 0.15 or less and its impurity concentration is I x 10"/Cm3 or more. Note that a second electrode force is formed on the back surface of the substrate 21. .

この素子の製造方法は次の通りである。まずGaAs基
板21 f=n型GaAa層nを約5μm成長させる。
The method for manufacturing this element is as follows. First, a GaAs substrate 21 f=n type GaAa layer n is grown to a thickness of about 5 μm.

成長方法は液相エピタキシャル成長法、気相エピタキシ
ャル成長法いずれでもよい。例えば液相の場合、Toと
GaAsを含むGa融液を830 Cm後の濃度で基板
21に廣工させに状態で保冷すること(=より得られる
The growth method may be either a liquid phase epitaxial growth method or a vapor phase epitaxial growth method. For example, in the case of a liquid phase, a Ga melt containing To and GaAs is spread over the substrate 21 at a concentration of 830 Cm and kept cool.

久に周知のPEP技術を利用して電流路となるべき部分
に開口を持つマスクを形成し、Znを選択拡散してn型
GaAa盾Uの一部(=p W GaAa着乙を形成す
る。これにより発光素子を形成する定めの基体が得られ
る。この仮液相エビメ千シャル成長(=よp発光層を形
成する。即ち、複数の半導体融液溜を設けたエピタキシ
ャルボートを用意し、Gd液溜には必要な結晶を成長さ
せるための融液を順次並べて仕込む。例えば、第1融g
、溜には、Ga100y 、 GaAs 7.5P 、
 kl 15LJ u’?、 Ge 3 tを仕込み、
第2融液溜(=は、Ga IIJQ f 、 GaAs
 7.5 f 、 AJ 15ダ、Ge3gを仕込み、
第3融液1には、Ga lυUt + GaAa 7.
5 f 、 Al15071+9. Te 6m9を仕
込み、第4融液溜(ユは、Ga 1tlOy 、 Ga
Aa 7.5 t、 kl 35”Si’ + To 
5++19  を仕込み、第5融液層(=はGa 10
0y。
Using the well-known PEP technology, a mask with openings is formed in the portion that is to become the current path, and Zn is selectively diffused to form a part of the n-type GaAa shield U (=p W GaAa deposit). As a result, a predetermined substrate on which a light-emitting element is formed is obtained.A light-emitting layer is formed by this pseudo-liquid phase emissive growth.In other words, an epitaxial boat equipped with a plurality of semiconductor melt reservoirs is prepared, and The melts for growing the necessary crystals are sequentially arranged in the liquid reservoir.For example, the first melt g
, the reservoir contains Ga100y, GaAs 7.5P,
kl 15LJ u'? , prepare Ge3t,
Second melt reservoir (=, Ga IIJQ f, GaAs
7.5 f, AJ 15 da, Ge3g prepared,
The third melt 1 contains GalυUt + GaAa7.
5f, Al15071+9. 6m9 of Te was charged, and the fourth melt reservoir (Y, Ga 1tlOy, Ga
Aa 7.5t, kl 35"Si' + To
5++19 is charged, and the fifth melt layer (= is Ga 10
0y.

GaAs 25 y 、 Te 61119を仕込む。GaAs 25y, Te 61119 are charged.

これらの融液溜と基体とを、約850℃(=昇温した後
、冷却速fl’c7分の徐冷中にそれぞれ接触1分離を
繰返して結晶成長を行ない、第2図(=示すよう(=p
型GaAlAsクラッド7’J 24 、 P m−G
aAAAs活性7m25.nEず1GaAlAsり2ツ
ド膚が1光取9出し層となるn型GaAlAs +ci
 27 + n型GaAsキャップ層28(不純!#磯
度は1 x 10”7m”以上)を落成する。
After raising the temperature of these melt reservoirs and the substrate to approximately 850°C (=), crystal growth was performed by repeating contact and separation for each during slow cooling at a cooling rate of 7 minutes, as shown in Figure 2 (= p
Type GaAlAs clad 7'J 24 , P m-G
aAAAs activity 7m25. n-type GaAlAs +ci where the layer is 1 light extraction layer.
27 + n-type GaAs cap layer 28 (impure!# roughness is 1 x 10"7 m" or more) is completed.

前述のようにGaAJAsノラッド虐24,24のAA
組成比はGaAlAa活性層5のそれの約6〜10倍と
なシ、ダブルへテロ償金が形成される。また光取出し層
となるn M GaAJAs ItsのAl(0m成は
Ga1−、A4Asとして表わした時、Xが0.15以
下で、本実施例の場合は0.1とした。さらにこのn 
W GaAlAs層の不純物、a度はI X 10”/
テ以上とし、本実施例の場合は5 X 10”/鑞3と
した。
As mentioned above, GaAJAs Norad 24, 24's AA
When the composition ratio is about 6 to 10 times that of the GaAlAa active layer 5, a double heterogeneous layer is formed. In addition, when Al of n M GaAJAs Its which becomes the light extraction layer (0 m composition is expressed as Ga1-, A4 As,
Impurity of W GaAlAs layer, a degree is I x 10”/
In this example, it was 5 x 10"/3 solders.

この後、TI+型GaAs キャップ;曽あの表面に、
PEP技術を利用して光取出し部に回目を持つマスクパ
ターンを形成し、アンモニア水と水と過酸化水素水から
なる混液で選択エツチングを行ない、n+型GaAs層
のみを除去して、これを光取出し窓31とする。第1の
(1四はAuGe合蛍により、また第2の電極30はA
uZn合金によりそれぞれ形成する。
After this, a TI+ type GaAs cap;
Using PEP technology, a patterned mask pattern is formed in the light extraction area, and selective etching is performed using a mixture of ammonia water, water, and hydrogen peroxide to remove only the n+ type GaAs layer, which is exposed to light. It is assumed that the extraction window 31 is used. The first electrode 14 is made of AuGe, and the second electrode 30 is made of AuGe.
Each is formed from a uZn alloy.

このように構成された発光素子は、第1.第2の磁極四
、30間に約2Vのj績方同−圧を印加して点光源(=
近い高輝度の発光が得られた二このよう(=高輝度の発
光が得られる理由としては、光取出し層となるn型Ga
AlAs層の不縄物蹟度をI X 10”/cIrL3
以上と高くしている為、n型GaAlA3クラッド層を
斜め(=横切って流れることが少なく、笑質的な電流路
は縦方向になって、発光素子の励作屯土を低くすること
ができるからと考えられる。また光取出し窓をGaAl
As j軸で構成している局、GaAsで構成するより
は光の吸収が少なくなる為、実質的な発光効率は低下し
ないものと考えられる。尚光取出し窓として用いるGa
AAAs itl<のAlの組成を多くした場合、Al
の酸化等、別の問題が種々発生するので、AIの組成は
Ga1−、AJ工Asで表わした場合X≦0.15が望
ましい。
The light emitting device configured in this way has the following structure. A voltage of approximately 2V is applied between the second magnetic poles 4 and 30, and a point light source (=
The reason for the high luminance emission is that the n-type Ga which becomes the light extraction layer
The roughness of the AlAs layer is I x 10”/cIrL3
Because the height is set as above, it is unlikely that the current will flow diagonally (= across) the n-type GaAlA3 cladding layer, and the negative current path will be in the vertical direction, making it possible to lower the excitation rate of the light-emitting element. It is thought that the light extraction window was made of GaAl.
Since the station constructed with As j-axis absorbs less light than the one constructed with GaAs, it is thought that the actual luminous efficiency will not decrease. Ga used as a light extraction window
When the Al composition of AAAs itl< is increased, Al
Since various other problems such as oxidation of aluminum occur, it is preferable that the composition of AI is X≦0.15 when expressed as Ga1- and AJ-As.

以上では、GaAs基板を用いたが、GaAlAs M
板を用いることもできる。また、活性層がnuGaAs
であってもよいし、磁流狭窄層がGaAlAsであって
もよい。その他本発明は、その趣旨を逸脱しない範囲で
種々変形実施することができる1゜
In the above, a GaAs substrate was used, but GaAlAs M
A plate can also be used. In addition, the active layer is made of nuGaAs.
Alternatively, the magnetic current confinement layer may be made of GaAlAs. In addition, the present invention can be modified in various ways without departing from its spirit.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の実施例の発光素子を示す図、第2図は
従来のダブルへテロ接合を用いた面発光の発光素子を示
す図である。 21 ・−p型GaAs基板 n・・・n W GaAs層(磁流狭窄層)お・・・p
型GaAa層 24・・・p型GaAlAsクラッド層δ・・・p型G
aAlAs活性層 26・・・n型GaAAAsクラッド層27 ・、 n
型GaAlAs itAあ・・・n型GaAsキャップ
層 四・・・第1の電極 (資)・・・第2の電極 31 ・・・光取出し窓(n型GaAlA、a )代理
人 弁理士 則 近 憲 右(ほか1名)第1図 3θ 第2図
FIG. 1 is a diagram showing a light emitting device according to an embodiment of the present invention, and FIG. 2 is a diagram showing a surface emitting light emitting device using a conventional double heterojunction. 21 ・-p-type GaAs substrate n...n W GaAs layer (magnetic current confinement layer)...p
Type GaAa layer 24...p type GaAlAs cladding layer δ...p type G
aAlAs active layer 26...n-type GaAAAs cladding layer 27...n
Type GaAlAs itA...N-type GaAs cap layer 4...First electrode (capital)...Second electrode 31...Light extraction window (n-type GaAlA, a) Agent Patent attorney Nori Chika Ken, right (and 1 other person) Figure 1 3θ Figure 2

Claims (1)

【特許請求の範囲】[Claims]  第1導電型GaAsまたはGaAlAs基板に電流狭
窄層が選択的に設けられ、この上にダブルヘテロ接合を
有する発光層が形成され、この発光層の表面にAl濃度
の低いGaAlAs層を形成し、さらにその表面にGa
Asキャップ層を介して第1の電極が、前記基板裏面に
第2の電極がそれぞれ形成され、前記第1の電極側にA
l濃度の低いGa_1_−_xAl_xAs層を光取り
出し窓とする半導体発光素子において前記光取り出し窓
のGa_1_−_xAl_xAs層のAl比をx≦0.
15とし、不純物濃度を1×10^1^8/cm^3以
上とすることを特徴とする半導体発光素子。
A current confinement layer is selectively provided on a first conductivity type GaAs or GaAlAs substrate, a light emitting layer having a double heterojunction is formed thereon, a GaAlAs layer with a low Al concentration is formed on the surface of this light emitting layer, and Ga on its surface
A first electrode is formed through an As cap layer, a second electrode is formed on the back surface of the substrate, and an A cap layer is formed on the first electrode side.
In a semiconductor light emitting device using a Ga_1_-_xAl_xAs layer with a low l concentration as a light extraction window, the Al ratio of the Ga_1_-_xAl_xAs layer of the light extraction window is set to x≦0.
15 and an impurity concentration of 1×10^1^8/cm^3 or more.
JP59193960A 1984-09-18 1984-09-18 Semiconductor light-emitting element Pending JPS6173388A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59193960A JPS6173388A (en) 1984-09-18 1984-09-18 Semiconductor light-emitting element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59193960A JPS6173388A (en) 1984-09-18 1984-09-18 Semiconductor light-emitting element

Publications (1)

Publication Number Publication Date
JPS6173388A true JPS6173388A (en) 1986-04-15

Family

ID=16316622

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59193960A Pending JPS6173388A (en) 1984-09-18 1984-09-18 Semiconductor light-emitting element

Country Status (1)

Country Link
JP (1) JPS6173388A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63124592A (en) * 1986-11-14 1988-05-28 Nec Corp Semiconductor laser device
JPH03171679A (en) * 1989-11-29 1991-07-25 Toshiba Corp Semiconductor light emitting device
CN109873046A (en) * 2019-01-28 2019-06-11 电子科技大学 Double heterojunction photodiode and preparation method

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5598775U (en) * 1978-12-29 1980-07-09
JPS5888366U (en) * 1981-12-09 1983-06-15 株式会社資生堂 Wet tissue storage equipment

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5598775U (en) * 1978-12-29 1980-07-09
JPS5888366U (en) * 1981-12-09 1983-06-15 株式会社資生堂 Wet tissue storage equipment

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63124592A (en) * 1986-11-14 1988-05-28 Nec Corp Semiconductor laser device
JPH0587157B2 (en) * 1986-11-14 1993-12-15 Nippon Electric Co
JPH03171679A (en) * 1989-11-29 1991-07-25 Toshiba Corp Semiconductor light emitting device
JPH06103759B2 (en) * 1989-11-29 1994-12-14 株式会社東芝 Semiconductor light emitting device
CN109873046A (en) * 2019-01-28 2019-06-11 电子科技大学 Double heterojunction photodiode and preparation method
CN109873046B (en) * 2019-01-28 2020-09-11 电子科技大学 Double-heterojunction photosensitive diode and preparation method thereof

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