JPS6173353A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6173353A JPS6173353A JP59194665A JP19466584A JPS6173353A JP S6173353 A JPS6173353 A JP S6173353A JP 59194665 A JP59194665 A JP 59194665A JP 19466584 A JP19466584 A JP 19466584A JP S6173353 A JPS6173353 A JP S6173353A
- Authority
- JP
- Japan
- Prior art keywords
- sealing body
- lead
- resin
- resin sealing
- package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
- H05K3/3478—Applying solder preforms; Transferring prefabricated solder patterns
Abstract
Description
【発明の詳細な説明】
〔技術分野〕
本発明は半導体装置に関し、特Ｋ、当該装置のパッケー
ジング技術に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a semiconductor device, and particularly to a packaging technique for the device.
半導体装置の高集積化九伴って外部リード端子数も増加
し、いわゆる多ビン（端子）化の傾向にある。As semiconductor devices become more highly integrated, the number of external lead terminals also increases, and there is a trend toward so-called multi-bin (terminal) design.
多ビン化により、リード（ピン）間隔は増々狭くなり、
リード巾も小さくなってきている。これにより、リード
強度が弱くなり、かつ、プリント基板などの実装基板へ
の実装時やその取扱上、リード曲りを生じたり、あるい
はコンタクト不良を生じたりする。With the increase in the number of bins, the lead (pin) spacing is becoming narrower and narrower.
Lead width is also becoming smaller. This weakens the lead strength, and also causes lead bending or contact failure during mounting on a mounting board such as a printed circuit board or during handling thereof.
特に、プリント基板などの実装基板への実装密度を高め
るためＫ、ピン間隔を狭くシテパソケージ本体の両側ま
たは四方向忙多数の端子（アウターリード）を出し、プ
リント基板の孔に挿入せずに当該基板の導体パターンに
直接平面付けするタイプの小形フラットバック型パッケ
ージにあっては、上記リード曲りなどが顕著である。In particular, in order to increase the mounting density on a mounting board such as a printed circuit board, the pin spacing is narrowed, and a large number of terminals (outer leads) are brought out on both sides of the cage body or in all four directions, without being inserted into the holes of the printed circuit board. In small flat-back type packages that are directly attached to the conductor pattern, the above-mentioned lead bending is noticeable.
なお、フラットパンク型パッケージのリードの寸法は、
たとえば、サイエンスフォーラム社発行、ｍＬｓＩデバ
イスハンドブック、昭和５８年１１月２８日発行、Ｐ２
２５に示されている。The dimensions of the leads of the flat punk package are as follows:
For example, published by Science Forum, mLsI Device Handbook, November 28, 1980, P2
25.
本発明は、リード曲りなどの上記した不良を防止し、多
ピン化の要請に答えることのできろ半導体装置を提供す
ることを目的とする。SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device that can prevent the above-mentioned defects such as lead bending and can meet the demand for increased pin count.
本発明の前記ならびにそのほかの目的と新規な特徴は、
本明細書の記述および添付図面からあきらかになるであ
ろう。The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.
本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、下記のとおりである。A brief overview of typical inventions disclosed in this application is as follows.
すなわち、アウターリードをパッケージ外部に出さない
ようにし、パッケージ製造時にアウターリードを切断し
たプラスチックパッケージとし、パッケージ内にはイン
ナーリードのみを配し、このパッケージ内部のインナー
リードと外部と導通をとるために、パッケージ底面に、
インナーリードと連通する穴を穿設し、該穴に半田を取
付するものである。In other words, the outer leads are not exposed to the outside of the package, the outer leads are cut off during package manufacturing, and the package is made of plastic.Only the inner leads are placed inside the package, and the inner leads inside the package are electrically connected to the outside. , on the bottom of the package.
A hole communicating with the inner lead is bored and solder is attached to the hole.
〔実施例１〕 第１図に示すような多連のリードフレームを用意する。[Example 1] Prepare multiple lead frames as shown in FIG.
第１図にて、１は半導体素子搭載のための半導体素子搭
載部（タブ）、２はリードフレームの外枠である。３は
インナーリード、４はアウターリードである。In FIG. 1, 1 is a semiconductor element mounting portion (tab) for mounting a semiconductor element, and 2 is an outer frame of a lead frame. 3 is an inner lead, and 4 is an outer lead.
これらリードは、パッケージングした場合、パッケージ
両側から配列されていても、四方向から配列されていて
もよいが、四方向から配列されていることが多ピン化の
要求からは望ましい。When packaged, these leads may be arranged from both sides of the package or from all four directions, but it is desirable to arrange them from all four directions in view of the need for a large number of pins.
第１図ではＤＩＬ（デュアル・イン・ライン）タイプの
ものを図示しである。FIG. 1 shows a DIL (dual in line) type.
四角形状のタブ１上に四角形状の半導体素子をＡｕ−８
ｔ共晶法などの周知のペレット付法によりマウント（固
着）する。そして、該半導体素子とインナーリード３と
をコネクタワイヤにより周知の例えば超音波ボンディン
グ法によりボンディングする。A square-shaped semiconductor element is placed on the square-shaped tab 1 using Au-8.
Mount (fix) using a well-known pellet attachment method such as the eutectic method. Then, the semiconductor element and the inner lead 3 are bonded using a connector wire by a well-known method such as ultrasonic bonding.
かかるペレット付（グイボンディング）およびワイヤボ
ンディング後、例えばトランスファーモールド法などの
レジンモールド法により半導体素子やワイヤボンディン
グ部などを例えばエポキシ樹脂などの樹脂により封止す
る。After such pellet bonding and wire bonding, the semiconductor element, wire bonding portion, etc. are sealed with a resin such as epoxy resin by a resin molding method such as a transfer molding method.
樹脂封止後忙アウターリード４を切断する。After resin sealing, the outer leads 4 are cut.
一般に、樹脂封止型半導体装置は多連のり−ト。Generally, resin-sealed semiconductor devices are multi-glued.
フレームに半導体チップをマウントし、ワイヤボンディ
ングした後、モールド金型忙入れて樹脂でトランスファ
ーモールドし、アウターリードを切断せずにそのまま残
し、次いでアウターリードを折曲げしているが、本発明
では第１図に示すＩ−エ線（横方向の切断のみ示してい
る）で切断し、アウターリードをカットしてしまう。After mounting the semiconductor chip on the frame and wire bonding, transfer molding is performed using resin in a mold, leaving the outer leads as they are without cutting them, and then bending the outer leads. The outer lead is cut by cutting along the I-E line shown in Figure 1 (only the lateral cutting is shown).
樹脂封止後の当該パッケージの第１図■−■線に沿う断
面図を第２図に示した。FIG. 2 shows a cross-sectional view of the package after resin sealing, taken along the line ■--■ in FIG. 1.
第２図にて、５は半導体素子、６は当該素子の電極（パ
ッド）、７はコネクタワイヤ、８は樹脂封止体である。In FIG. 2, 5 is a semiconductor element, 6 is an electrode (pad) of the element, 7 is a connector wire, and 8 is a resin sealing body.
ところで、前記第１図にて、９はダムであり、樹脂封止
の際にリードを固定し、樹脂の流れを阻止するためのも
のである。本発明では一般にリードフレームを構成して
いるダムを用いてもよいが、テープを用いることがよい
。すなわち、リードをテーピングし、固定しておくとよ
い。Incidentally, in FIG. 1, numeral 9 is a dam, which is used to fix the leads and prevent the flow of resin during resin sealing. In the present invention, a dam, which generally constitutes a lead frame, may be used, but it is preferable to use a tape. In other words, it is better to tape the leads and fix them.
樹脂封止後に、樹脂封止体の底面に穴を穿設する。樹脂
封止の際に同時に当該穴の形成を行なっていてもよい。After resin sealing, a hole is bored in the bottom of the resin sealing body. The hole may be formed at the same time as the resin sealing.
第３図は穴を設けて成る当該装置の底面図を示す。第３
図にて、８は樹脂封止体、１０は上記穴を示し、また、
１１はパッケージ吊り部を示す。パッケージ吊り部１１
は、樹脂封止体８を、リードフレームの外枠２（第１図
）に吊った状態にしておき、かつ、第１図に示すように
、半導体素子搭載部１を支持するものである。FIG. 3 shows a bottom view of the device provided with holes. Third
In the figure, 8 indicates the resin sealing body, 10 indicates the above-mentioned hole, and
11 indicates a package hanging part. Package hanging part 11
The resin sealing body 8 is suspended from the outer frame 2 of the lead frame (FIG. 1), and as shown in FIG. 1, the semiconductor element mounting portion 1 is supported.
外枠２にパッケージ吊り部１１により吊り下げられ、底
面に穴の開けられたパッケージを、次℃・で、当該吊り
部１１を切断し、単体に分離する。The package, which is suspended from the outer frame 2 by the package hanging part 11 and has a hole in the bottom surface, is then separated into individual pieces by cutting the hanging part 11 at .degree.
穴１０は樹脂封止体８内部のインナーリード３にまで到
着するように設けられている。The hole 10 is provided so as to reach the inner lead 3 inside the resin sealing body 8.
この穴１０に、次に、半田粒を取付ける。Next, solder grains are attached to this hole 10.
第４図は当該半田粒を取付けて成る樹脂封止型半導体装
置の断面図を示し、また、第４図には当該装置の実装基
板への実装の様子を示しである。FIG. 4 shows a sectional view of a resin-sealed semiconductor device with the solder particles attached thereto, and also shows how the device is mounted on a mounting board.
第４図にて、第１図〜第３図に共通する符号は同一の機
能を示すので、その説明を省略するが、第４図にて、１
２は当該半田粒を示し、また、１３は実装基板を示す。In FIG. 4, the symbols common to FIGS. 1 to 3 indicate the same functions, so their explanation will be omitted.
2 indicates the solder grain, and 13 indicates the mounting board.
その実装は、半田粒１２を溶融させることにより行うこ
とができる。したがって、半田粒１２は第４図に示すよ
うに、穴１０から一部が突出しするように取付ける。The mounting can be performed by melting the solder grains 12. Therefore, the solder grains 12 are attached so that a portion thereof protrudes from the hole 10, as shown in FIG.
本発明に使用されるリードフレームは例えば４２７０イ
により構成されるが、テーピングの場合のテープ罠は例
えば、ポリイミドテープなどの樹脂テープを使用すると
よい。また、パッケージ吊り部１１も同様に例えば樹脂
テープにより構成される。The lead frame used in the present invention is made of, for example, 4270I, but for the tape trap in the case of taping, it is preferable to use, for example, a resin tape such as polyimide tape. Further, the package hanging portion 11 is similarly made of, for example, a resin tape.
半導体素子５は、例えばシリコーン単結晶基板から成り
、周知の技術によってこのチップ内には多数の回路素子
が形成され、１つの回路機能が与えられている。回路素
子の具体例は、例えばＭＯＳトランジスタから成り、こ
れらの回路素子によって、例えばメモリや論理回路の回
路機能が形成されて℃・る。The semiconductor element 5 is made of, for example, a silicon single crystal substrate, and a large number of circuit elements are formed within this chip using well-known techniques to provide one circuit function. A specific example of the circuit element is, for example, a MOS transistor, and these circuit elements form a circuit function such as a memory or a logic circuit.
バッド６は、例えばＡ２電極により構成される。The pad 6 is composed of, for example, an A2 electrode.
コネクタワイヤ７は例えばＡｕ線やＡ−ｇ線により構成
される。The connector wire 7 is made of, for example, an Au wire or an Ag wire.
〔実施例２〕 次に、本発明の他の実施例を示す。[Example 2] Next, other embodiments of the present invention will be shown.
第５図に示すような多連のテープキャリアを用意する。A series of tape carriers as shown in FIG. 5 is prepared.
このテープキャリアは、例えばポリイミドテープにより
構成されている。This tape carrier is made of, for example, polyimide tape.
このテープキャリアの形成は周知のテープキャリア方式
によればよい。This tape carrier may be formed by a well-known tape carrier method.
半導体チップの電極位置忙合せリードパターンを樹脂製
テープ例えばポリイミドテープ上に例えば銅箔を接着剤
によりラミネートし、バターニングして形成する。A lead pattern for adjusting the electrode positions of a semiconductor chip is formed by laminating, for example, a copper foil on a resin tape, for example, a polyimide tape, with an adhesive, and then patterning it.
第５図忙て、１４はポリイミドテープ、１５は銅箔によ
り形成されたリードパターンを示し、リード１５先端が
半導体チップをダイボンディングするためのデバイスホ
ール１６内に突出している。In FIG. 5, numeral 14 indicates a lead pattern formed of polyimide tape and numeral 15 a lead pattern formed of copper foil, and the tip of the lead 15 projects into a device hole 16 for die-bonding a semiconductor chip.
ポリイミドテープ１４にはスプケノトホール１７がパン
チングされ、連続的に半導体素子が組込みされるように
なっている。Spoke holes 17 are punched in the polyimide tape 14 so that semiconductor elements can be successively incorporated therein.
第５図ではその図示が省略されているが、前記実施例１
と同様にパッケージ吊り部がポリイミドテープにより形
成されている。Although illustration thereof is omitted in FIG. 5, the above embodiment 1
Similarly, the package hanging part is made of polyimide tape.
かかるテープキャリアに半導体素子（図示せず）を、そ
の電極（図示せず）を介してリード１５にダイボンディ
ングする。A semiconductor element (not shown) is die-bonded to the lead 15 via the electrode (not shown) of the semiconductor element (not shown).
ダイボンディング（インナーリードボンディング）後に
、レジンモールドする。After die bonding (inner lead bonding), resin molding is performed.
パッケージ吊り部を残して、アウターリードを切断し、
その後、パッケージ吊り部を切断して単体に分離する。Cut the outer leads leaving the package hanging part,
Thereafter, the package hanging portion is cut and separated into individual pieces.
前記実施例１と同様にして樹脂封止体の底面には穴が設
けられている。Similar to the first embodiment, holes are provided in the bottom surface of the resin sealing body.
この穴に半田粒を取付け、リードと接続する。Attach a solder grain to this hole and connect it to the lead.
リード底面（大側）にはメタライズ層を形成し、半田粒
との電気的接続を良好ならしめるようにしてお（とよい
。It is preferable to form a metallized layer on the bottom surface (large side) of the lead to ensure good electrical connection with the solder grains.
（１）本発明によれば、従来のフラットパックパッケー
ジの如く、中小でピッチ狭の多数のアウターリードをパ
ンケージ外部に配出せず、樹脂封止体に穴を設けてそこ
に半田粒を入れるようにしだので、リード曲りの発生を
阻止することができた。(1) According to the present invention, unlike conventional flat pack packages, it is not necessary to arrange a large number of small and medium-sized outer leads with a narrow pitch to the outside of the pan cage. Since it was made of wood, it was possible to prevent the lead from bending.
（２）上記の如（半田粒により実装基板に実装するよう
にしたので、その実装も容易で、コンタクト不良を回避
することができた。(2) As described above, since it was mounted on the mounting board using solder particles, the mounting was easy and contact failures could be avoided.
（３）本発明半導体装置は半田粒を取付けた構造のもの
であるので、従来の足の長いアウターリードカパッケー
ジ外部から配出したものに比してその取扱がきわめて容
易である。(3) Since the semiconductor device of the present invention has a structure in which solder grains are attached, it is much easier to handle than the conventional semiconductor device which is delivered from the outside of the long-legged outer lead package.
（４）本発明半導体装置を実装基板に実装する場合、そ
の基板への位置決めは、パッケージ本体で行なえるため
（アウターリードがない）、自動基板実装を可能とする
。(4) When the semiconductor device of the present invention is mounted on a mounting board, the positioning on the board can be performed using the package body (there is no outer lead), so automatic board mounting is possible.
（５）本発明ではパッケージ底面にて端子数を増加でき
るので多ビン化が可能である。(5) In the present invention, since the number of terminals can be increased on the bottom surface of the package, it is possible to increase the number of bins.
以上本発明者によってなされた発明を実施例にもとづき
具体的に説明したが、本発明は上記実施例に限定される
ものではな（、その要旨を逸脱しない範囲で種々変更可
能であることはいうまでもない。Although the invention made by the present inventor has been specifically explained above based on examples, the present invention is not limited to the above-mentioned examples (although it is possible to make various changes without departing from the gist of the invention). Not even.
例えば前記実施例ではフラットバックタイプのプラスチ
ックパッケージ、及びテープキャリアタイプのプラスチ
ックパッケージ忙ついて示したが、多層配線を有するプ
リント基板に同様に本発明を適用して、多層配線圧より
リードの引きまわしをはかることにより、より一層多ビ
ン化することが可能である。For example, in the above embodiment, a flat back type plastic package and a tape carrier type plastic package were shown, but the present invention can be similarly applied to a printed circuit board with multilayer wiring to reduce the lead routing due to the multilayer wiring pressure. By measuring, it is possible to create even more bins.
本発明は広くプラスチックパッケージに適用でき、さら
Ｋは、各種電子部品のパッケージにも適用できる。The present invention can be widely applied to plastic packages, and can also be applied to packages for various electronic components.
第１図は本発明に使用される多連のリードフレームの一
部を例示する平面図、
第２図は本発明実施例工程を説明する要部断面図、
第３図は本発明実施例工程を説明する底面図、第４図は
本発明実施例を示す断面図、
第５図は本発明に使用されるテープキャリアの一例平面
図である。
１・・・半導体素子搭載部、２・・・リードフレーム外
枠、３・・・インナーリード、４・・・アウターリード
、５・・・半導体素子、６・・・電極、７・・・コネク
タワイヤ、８・・・樹脂封止体、９・・・テープ、１０
・・・穴、１１・・・パッケージ吊り部、１２・・・半
田粒、１３・・・実装基板、１４・・・ポリイミドテー
プ、１５・・・リードバター／、１６・・・テハイスホ
ール、１７・・・スプロケットホール。Fig. 1 is a plan view illustrating a part of a multi-lead frame used in the present invention, Fig. 2 is a cross-sectional view of main parts explaining the steps of the embodiment of the present invention, and Fig. 3 is the process of the embodiment of the present invention. FIG. 4 is a sectional view showing an embodiment of the present invention, and FIG. 5 is a plan view of an example of a tape carrier used in the present invention. DESCRIPTION OF SYMBOLS 1... Semiconductor element mounting part, 2... Lead frame outer frame, 3... Inner lead, 4... Outer lead, 5... Semiconductor element, 6... Electrode, 7... Connector Wire, 8... Resin sealing body, 9... Tape, 10
... Hole, 11... Package hanging part, 12... Solder grain, 13... Mounting board, 14... Polyimide tape, 15... Lead butter/, 16... Tech high speed hole, 17... ... Sprocket hole.
Claims (1)
脂封止体に設けられた穴に前記半導体素子と当該封止体
外部との導通をとり、かつ、実装基板への実装のための
導体部を付着して成ることを特徴とする樹脂封止型半導
体装置。 ２、前記導体部が、半田より成る、特許請求の範囲第１
項記載の半導体装置。[Claims] 1. A semiconductor element is fixed to a support body, sealed with a resin, and conduction is established between the semiconductor element and the outside of the sealed body through a hole provided in the resin sealed body, and A resin-sealed semiconductor device characterized by having a conductor portion attached thereto for mounting on a mounting board. 2. Claim 1, wherein the conductor portion is made of solder.
1. Semiconductor device described in Section 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59194665A JPS6173353A (en) | 1984-09-19 | 1984-09-19 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59194665A JPS6173353A (en) | 1984-09-19 | 1984-09-19 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6173353A true JPS6173353A (en) | 1986-04-15 |
Family
ID=16328271
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59194665A Pending JPS6173353A (en) | 1984-09-19 | 1984-09-19 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6173353A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5608265A (en) * | 1993-03-17 | 1997-03-04 | Hitachi, Ltd. | Encapsulated semiconductor device package having holes for electrically conductive material |
-
1984
- 1984-09-19 JP JP59194665A patent/JPS6173353A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5608265A (en) * | 1993-03-17 | 1997-03-04 | Hitachi, Ltd. | Encapsulated semiconductor device package having holes for electrically conductive material |
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