JPS6173339A - Wire bonding method - Google Patents
Wire bonding methodInfo
- Publication number
- JPS6173339A JPS6173339A JP59194028A JP19402884A JPS6173339A JP S6173339 A JPS6173339 A JP S6173339A JP 59194028 A JP59194028 A JP 59194028A JP 19402884 A JP19402884 A JP 19402884A JP S6173339 A JPS6173339 A JP S6173339A
- Authority
- JP
- Japan
- Prior art keywords
- bonding
- semiconductor chip
- electrode pad
- electrode pads
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
- H01L24/78—Apparatus for connecting with wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/78—Apparatus for connecting with wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/78—Apparatus for connecting with wire connectors
- H01L2224/7825—Means for applying energy, e.g. heating means
- H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
- H01L2224/78301—Capillary
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8512—Aligning
- H01L2224/85148—Aligning involving movement of a part of the bonding apparatus
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12041—LED
Abstract
Description
【発明の詳細な説明】
［発明の技術分野１
この発明は半導体装置のワイ（７ボンデイング方法に関
し、特に、従来方法よりも迅速にボンデＣレグを行うこ
とができ且つボンディング不良等を生ずる恐れのない、
改良されたワイヤボンディング方法に関するものである
。Detailed Description of the Invention [Technical Field of the Invention 1] The present invention relates to a method for bonding semiconductor devices, and in particular, it is capable of performing a bonding C leg more quickly than conventional methods, and is capable of eliminating the risk of bonding defects. do not have,
The present invention relates to an improved wire bonding method.
［発明の技術的背景１
従来使用されているワイヤホンダにａ５いては、第５図
に示すようにボンディングアーム１のＴ２９Ｗ部にレバ
ー２を設けておぎ、ボンディング時にキャピラリ３が半
導体チップ４の電極パッド上に接触しｌ〔時に該レバー
２がマイクロスイッチ作動アーム５を作動させることに
よりキ【／ピラリ３と半導体チップ４の電極パッドとが
接触したことを検出し、マイクロスイッチ作動アーム５
に対する該レバー２の位置１ｉ１１１１ｔをすることに
よりキレピラリ沈の電極パッド部への沈み込みｍを制御
している。[Technical Background of the Invention 1] In the conventionally used wire honda A5, a lever 2 is provided at the T29W portion of the bonding arm 1 as shown in FIG. When the lever 2 contacts the pad, the lever 2 activates the microswitch actuation arm 5 to detect the contact between the pillar 3 and the electrode pad of the semiconductor chip 4, and activates the microswitch actuation arm 5.
By adjusting the position 1i1111t of the lever 2 relative to the position 1i1111t, the sinking m of the sharp drop into the electrode pad portion is controlled.
また、前記のごとき構成の検出器の代りにボンディング
アーム１のヰ喘部もしくはギヤピラリ３の取付部に静電
容量形変位計を組み込／υで、電（咀バッドの高さ位置
やボンディング中の電極パッド部へのキレピラリ沈み込
み聞を検出Ｊるようにしたワイヤホンダもある。In addition, instead of the detector configured as described above, a capacitance type displacement meter is installed in the gap part of the bonding arm 1 or the mounting part of the gear pillar 3. There is also a wire Honda that detects the sharp sinking of the electrode pad into the electrode pad.
［前頭技術の問題点］
前記のごとき公知のワイヤポンダでは、キ１７ビラリと
半導体チップの電極パッドとの１幾械的接触を利用して
、電極パッドの高さ位置やボンディング中の半導体チッ
プへのキャピラリ沈下ｍを検出する接触式検出方法が採
用されているが、このような接触式検出方法を採用した
揚台、次のような。[Problems with Frontal Technology] In the known wire bonder as described above, the height position of the electrode pad and the contact with the semiconductor chip during bonding are determined by using the mechanical contact between the opening and the electrode pad of the semiconductor chip. A contact detection method for detecting capillary subsidence m has been adopted, and a lifting platform that employs such a contact detection method is as follows.
問題点があった。There was a problem.
（１） キ１１ピラリが電極パッドに接触して該電極パ
ッドの高さ位置が検出された後にボンディングが引き続
いて行われることになり、検出とポンディレグとが同一
ストローク中で行われるため、検出信号に基く演算処理
の時間が短い。 それ故、検出精度及びボンディングス
トロークの制御閉度が低くなり勝ちであり、従って各電
極パッド毎のボンディング状態が均等にならず、ボンデ
ィング不良を発生しやすい。(1) After the key 11 pillar comes into contact with the electrode pad and the height position of the electrode pad is detected, bonding is performed successively, and since detection and pound leg are performed during the same stroke, the detection signal The calculation processing time based on this is short. Therefore, the detection accuracy and the control closeness of the bonding stroke are likely to be low, and therefore the bonding state of each electrode pad is not equal, which tends to cause bonding defects.
（ｉ；） この方法においてはキャピラリが半導体チ
ップ上の電極パッドに接する時にはかなり低速でなけれ
ばならないので、異なった高さ位置にある多数の電極パ
ッドに対して一律にボンディングするために低速ストロ
ーク長を良くしなｌｊればならないが、低速ストローク
長が長いとボンディングの能率が低くなるため、前記従
来方法ではワイヤボンディング工程における能率向」−
を図ることができない。(i;) In this method, when the capillary comes into contact with the electrode pads on the semiconductor chip, the speed must be quite low. Therefore, in order to uniformly bond many electrode pads located at different height positions, the low-speed stroke length is required. However, if the low-speed stroke length is long, the bonding efficiency will decrease, so in the conventional method, the efficiency in the wire bonding process is reduced.
It is not possible to aim for
［発明の目的］
この発明の目的は、前記のごとき従来方法に存する問題
点を解決し、従来方法よりも迅速且つ確実にボンディン
グを行うことが′Ｃさるとともにボンディング不良等を
生ずる恐れの少ない改良されたワイヤボンディング方法
を提供することである。[Objective of the Invention] The object of the present invention is to solve the problems of the conventional method as described above, and to provide an improvement that allows bonding to be performed more quickly and reliably than the conventional method, and that reduces the risk of bonding defects. An object of the present invention is to provide a wire bonding method.
［発明の概要］
この発明による方法は、ボンディングに先立って半導体
チップのＱ１４ｉパッドのうち少なくとも３個の電極パ
ッドの高さを無接触で検出するとともにその検出値に基
いて該半導体チップの全電極パッドの高さ位置を演算し
、ボンディング時にはその演算結果に基いて個々の電極
パッドに対するボンディングヘッドの昇降動を制御する
ことを特徴とするものである。 また、この発明の方法
では、半導体チップの各電極パッドの高さ位置をキャピ
ラリと電極パッドとの機械的接触によらずに検出するの
で、電極パッドの高さ検出とボンディングとが分離され
、その結果、検出精度が向上して従来よりも確実な信頼
性の高いボンディングを行うことができるとともに従来
よりも迅速に且つ能率的にボンディングを行うことがで
きる。[Summary of the Invention] The method according to the present invention detects the heights of at least three electrode pads among the Q14i pads of a semiconductor chip without contact prior to bonding, and based on the detected values, the heights of all electrodes of the semiconductor chip. This method is characterized in that the height position of the pad is calculated, and during bonding, the vertical movement of the bonding head with respect to each electrode pad is controlled based on the calculation result. Furthermore, in the method of the present invention, the height position of each electrode pad of a semiconductor chip is detected without relying on mechanical contact between the capillary and the electrode pad, so the height detection of the electrode pad and bonding are separated, and the bonding is separated. As a result, detection accuracy is improved, and bonding can be performed more reliably and more reliably than in the past, and bonding can be performed more quickly and efficiently than in the past.
［発明の実施例コ
第１図は本発明を実施するための装置の一実施例を示し
たものである。 この実施例では、半導体チップ４上の
電極パッドの高さ位置を光学的に検出してその検出値に
基いてワイヤホンダのキャピラリの下降動を制御する場
合を示している。Embodiment of the Invention FIG. 1 shows an embodiment of an apparatus for carrying out the present invention. This embodiment shows a case where the height position of the electrode pad on the semiconductor chip 4 is optically detected and the downward movement of the capillary of the wire honda is controlled based on the detected value.
第１図において、７は従来のワイヤホンダに装備されて
いるテレビカメラ、８はテレビカメラ７の下端に設けら
れている鏡筒、９は鏡筒８内に収容された二つのハーフ
ミラ−１１０は発光ダイオード、１１は受光器である。In FIG. 1, reference numeral 7 denotes a television camera installed in a conventional wire Honda, 8 denotes a lens barrel provided at the lower end of the television camera 7, and 9 denotes two half mirrors 110 housed in the lens tube 8. A light emitting diode 11 is a light receiver.
ハーフミラ一つと発光ダイオード１０及び受光器１１
は本発明方法の実施のために従来のワイヤホンダのパタ
ーン認識）虚構の一部に付加的に組み込まれた部分であ
り、半導体チップ４上の電極パッドの高さ位置を光学的
に検出するための検出端を構成している。 受光器１１
は演算処理装置に電気的に接続されており、上方のハー
フミラ−９を通って受光器１１に入った光信号は受光器
１１で電気信号に変換された後、演算処理装置において
解析されて半導体チップ４上の各電極パッドの高さ位置
が求められる。One half mirror, light emitting diode 10 and light receiver 11
is a part additionally incorporated into a part of the conventional wire honda pattern recognition (pattern recognition) fabric for carrying out the method of the present invention, and is for optically detecting the height position of the electrode pad on the semiconductor chip 4. It constitutes the detection end of. Photoreceiver 11
is electrically connected to the arithmetic processing unit, and the optical signal that passes through the upper half mirror 9 and enters the photoreceiver 11 is converted into an electrical signal by the photoreceptor 11, and then analyzed in the arithmetic processing unit and sent to the semiconductor. The height position of each electrode pad on the chip 4 is determined.
本発明の方法においては、ボンディングに先立って、テ
レビカメラ７で半導体チップ４上のパターンを走査する
時に同時に発光ダイオード１０から発生する光を半導体
チップ４の電（セパラド上に投射してその反射光の情報
を演算処理装置で解析することにより、電極パッドの高
さ位置を求めておく。 そして、ワイヤボンディング工
程では、予め求めた電極パッドの高さ位置のデータに基
いてボンディングヘッド及びキャピラリのストロークを
制御しつつボンディングを行う。In the method of the present invention, prior to bonding, when the television camera 7 scans the pattern on the semiconductor chip 4, the light emitted from the light emitting diode 10 is simultaneously projected onto the semiconductor chip 4's electric field (separad), and the reflected light is detected. The height position of the electrode pad is determined by analyzing this information with a processing unit. Then, in the wire bonding process, the stroke of the bonding head and capillary is determined based on the data of the height position of the electrode pad determined in advance. Bonding is performed while controlling the
電極パッドの高さ位置の検出はすべての電（４パツドに
ついて行う必要はなく、三角形の頂ｒｒｊになる位置の
任なの３個の電極パッドか、らしくは、半導体チップの
四隅の電極パッドのみについて検出を行えばよい。 た
とえば第２図に示すように、半導体チップ４上の電極パ
ッド４１〜４３とキレピラリ３との間の高ざり、〜ｈ３
を検出し、この検出値に暴いて他のすべての電極パッド
の高さ位置を演算処理装置で演算する。It is not necessary to detect the height position of the electrode pads for all the electrode pads (it is not necessary to detect them for all four pads, but for any three electrode pads located at the apex rrj of the triangle, or perhaps only for the electrode pads at the four corners of the semiconductor chip). For example, as shown in FIG.
is detected, and based on this detected value, the height positions of all other electrode pads are calculated by a processing unit.
そして本発明方法のように、すべての電極パッドの高さ
位置が演算されると、ボンディングヘッド及びキレピラ
リの下降ストロークは各電極パッド毎に精密に時間の無
駄なく行うことができるので、各電極パッドにほぼ均等
な接合を形成することができるとともにボンディング工
程全体の作業速度を向上することができる。As in the method of the present invention, when the height positions of all electrode pads are calculated, the downward stroke of the bonding head and sharpening can be performed accurately for each electrode pad without wasting time. It is possible to form a substantially uniform bond and to improve the working speed of the entire bonding process.
［発明の効果］
第３図は従来の方法におけるキャピラリのもしくはボン
ディングヘッドの昇降ストロークの時間的経過を示す線
図であり、第４図は本発明におけるキレピラリもしくは
ボンディングヘッドの昇降ストロークの線図である。
同図において縦軸は上下方向移動量、横軸は時間経過を
表し、また、Ｔ、は高速下降時間、Ｔ２はサーチタイム
ずなわち定速（低速）下降時間、ＴＪは停止時間すなわ
らノバンドタイム、Ｔ４は高速上昇時間である。[Effects of the Invention] FIG. 3 is a diagram showing the elapse of time in the vertical stroke of the capillary or the bonding head in the conventional method, and FIG. 4 is a diagram showing the vertical stroke of the capillary or the bonding head in the present invention. be.
In the figure, the vertical axis represents vertical movement amount, the horizontal axis represents time elapsed, T is high-speed descent time, T2 is search time, that is, constant speed (slow speed) descent time, and TJ is stop time, that is, constant speed (low speed) descent time. The band time, T4, is the fast rise time.
更に、ａは高速下降から低速下降への切換点１なりちサ
ーチ点、ｂはキャピラリと半導体チップの電極パッドと
の接触点、Ｃは下降駆動力をｏｒｆ ７Ｊる点である。Furthermore, a is a search point which is the switching point 1 from high-speed descending to low-speed descending, b is a contact point between the capillary and the electrode pad of the semiconductor chip, and C is a point at which the descending driving force is applied.
第３図と第４図とを比較すると、本発明の方法では従来
の方法にくらべてサーチタイムＴ、が非常に狭くなり、
また、ａ点とｂ点との間のストロークＳが非常に小さく
なっていることがわかる。Comparing FIG. 3 and FIG. 4, the search time T is much narrower in the method of the present invention than in the conventional method.
It can also be seen that the stroke S between point a and point b is very small.
更に、ボンディング工程におけるキャピラリの全下降時
間が従来方法よりもかなり短くなっていることがわかる
。 その結果、本発明方法では従来方法にくらべて １
ワイヤ当りの平均インデックスを２０〜３０％短縮でき
る。Furthermore, it can be seen that the total capillary descent time during the bonding process is significantly shorter than in the conventional method. As a result, the method of the present invention has 1
The average index per wire can be reduced by 20-30%.
また、実験によれば、本発明の方法では従来方法よりも
各電極パッドの高さ位置を正確に締出することができ、
且つボンディング時にはボンディングヘッド及びキャピ
ラリの昇降動作を従来方法よりも精密に制御でき、その
結果、従来方法よりもばらつきの少ない加圧力を各電極
パッドに与えることができるとともにボンディング不良
を生ずる恐れの少ない安定した接合を作ることができる
ことがわかった。Also, according to experiments, the method of the present invention can more accurately lock out the height position of each electrode pad than the conventional method,
Furthermore, during bonding, the lifting and lowering movements of the bonding head and capillary can be controlled more precisely than in conventional methods, and as a result, it is possible to apply pressure to each electrode pad with less variation than in conventional methods, and to achieve stability with less risk of bonding defects. It was found that it was possible to create a bond that
以上に説明したように、この発明の方法によれば、従来
方法よりも迅速にワイヤボンディングを行うことができ
るとともにボンディング不良等を生ずる恐れの少ない高
信頼性の接合を形成することができる。 また、この発
明の方法では無接触で各電極パッドの高さ位置を検出す
るので耐衝撃性の低いＧａ ＡＳデバイスのワイヤボン
ディングに好適である。As described above, according to the method of the present invention, wire bonding can be performed more quickly than conventional methods, and highly reliable bonding can be formed with less risk of bonding defects. Furthermore, since the method of the present invention detects the height position of each electrode pad without contact, it is suitable for wire bonding of Ga AS devices with low impact resistance.
なお、実施例では光学的検出方法を用いる例のみを示し
たが、これ以外にも超音波による無接触検出方法を用い
てもよいことは当然である。In addition, although only the example which uses the optical detection method was shown in the Example, it is natural that a non-contact detection method using ultrasonic waves may be used in addition to this.
第１図は本発明方法を実Ｍするための装置の一例を示す
概略図、第２図は本発明方法の一実施例の概略図、第３
図は従来方法におけるボンディングヘッド及びキレピラ
リの昇降動線図、第４図は本発明方法におけるボンディ
ングヘッド及びキレピラリの昇降動線図、第５図は従来
のワイＡ７ボンダの概略図構造とｌ’ｒ ｉ！ＩＩＩの
説明図である。
１・・・ボンディングアーム、 ２・・・レバー、 ３
・・・キャピラリ、 ４・・・半導体チップ、 ５・
・・マイクロスイッチアーム、 ６・・・ボンディング
ヘッド、７・・・テレビカメラ、 ８・・・鏡筒、 ９
・・・ハーフミラ−１１０・・・発光ダイオード、 １
１・・・受光器、／１．１〜４３・・・電極パッド。
第１領
第２図
第３図 第４図
第５図FIG. 1 is a schematic diagram showing an example of an apparatus for carrying out the method of the present invention, FIG. 2 is a schematic diagram of an embodiment of the method of the present invention, and FIG.
Figure 4 is an upward and downward movement diagram of the bonding head and sharpness in the conventional method, Figure 4 is an upward and downward movement diagram of the bonding head and sharpness in the method of the present invention, and Figure 5 is a schematic diagram of the structure and structure of the conventional wire A7 bonder. i! It is an explanatory diagram of III. 1... Bonding arm, 2... Lever, 3
... Capillary, 4... Semiconductor chip, 5.
... Micro switch arm, 6... Bonding head, 7... Television camera, 8... Lens barrel, 9
... Half mirror 110 ... Light emitting diode, 1
1... Light receiver, /1.1-43... Electrode pad. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5
Claims (1)
ンディングに先立って半導体チップ上の電極パッドのう
ち少なくとも３個の電極パッドの高さを無接触で検出す
るとともにその検出値に基いて該半導体チップにおける
全電極パッドの高さを演算しておき、ボンディング時に
はその演算結果に基いて個々の電極パッドに対するボン
ディングヘッドの昇降動を制御することを特徴とするワ
イヤボンディング方法。1. In a wire bonding process for a semiconductor device, prior to bonding, the heights of at least three electrode pads on a semiconductor chip are detected without contact, and based on the detected values, all electrode pads on the semiconductor chip are A wire bonding method characterized in that the height of the bonding head is calculated in advance, and the vertical movement of a bonding head relative to each electrode pad is controlled based on the calculation result during bonding.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59194028A JPS6173339A (en) | 1984-09-18 | 1984-09-18 | Wire bonding method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59194028A JPS6173339A (en) | 1984-09-18 | 1984-09-18 | Wire bonding method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6173339A true JPS6173339A (en) | 1986-04-15 |
Family
ID=16317737
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59194028A Pending JPS6173339A (en) | 1984-09-18 | 1984-09-18 | Wire bonding method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6173339A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02125438A (en) * | 1988-11-04 | 1990-05-14 | Matsushita Electric Ind Co Ltd | Method for processing data of wire bonder |
| JPH039540A (en) * | 1989-06-07 | 1991-01-17 | Shinkawa Ltd | Wire bonding method |
| JPH05102236A (en) * | 1991-10-07 | 1993-04-23 | Kaijo Corp | Wirebonding device and method |
| JPH06181232A (en) * | 1992-12-15 | 1994-06-28 | Nec Corp | Wire bonder with automatic bonding level adjusting function |
| US5549716A (en) * | 1991-09-02 | 1996-08-27 | Tdk Corporation | Process for manufacturing integrated circuits using an automated multi-station apparatus including an adhesive dispenser and apparatus therefor |
| JPH08236573A (en) * | 1995-02-27 | 1996-09-13 | Nec Corp | Wire bonding device |
-
1984
- 1984-09-18 JP JP59194028A patent/JPS6173339A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02125438A (en) * | 1988-11-04 | 1990-05-14 | Matsushita Electric Ind Co Ltd | Method for processing data of wire bonder |
| JPH039540A (en) * | 1989-06-07 | 1991-01-17 | Shinkawa Ltd | Wire bonding method |
| US5549716A (en) * | 1991-09-02 | 1996-08-27 | Tdk Corporation | Process for manufacturing integrated circuits using an automated multi-station apparatus including an adhesive dispenser and apparatus therefor |
| JPH05102236A (en) * | 1991-10-07 | 1993-04-23 | Kaijo Corp | Wirebonding device and method |
| JPH06181232A (en) * | 1992-12-15 | 1994-06-28 | Nec Corp | Wire bonder with automatic bonding level adjusting function |
| JPH08236573A (en) * | 1995-02-27 | 1996-09-13 | Nec Corp | Wire bonding device |
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