JPS6120342A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6120342A JPS6120342A JP59140598A JP14059884A JPS6120342A JP S6120342 A JPS6120342 A JP S6120342A JP 59140598 A JP59140598 A JP 59140598A JP 14059884 A JP14059884 A JP 14059884A JP S6120342 A JPS6120342 A JP S6120342A
- Authority
- JP
- Japan
- Prior art keywords
- bonding
- bonding pad
- wire
- semiconductor chip
- head
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/78—Apparatus for connecting with wire connectors
- H01L2224/7825—Means for applying energy, e.g. heating means
- H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
- H01L2224/78301—Capillary
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
この発明は、半導体装置の製造方法に関し、更に詳細に
は半導体チップに対してワイヤボンディングを行う方法
に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of wire bonding a semiconductor chip.
［発明の技術的背景〕
リードフレームを用い半導体装置を組み立てる場合、第
４図のごときリードフレーム１のデツプマウントヘッド
１ａ上に第５図のように半導体チップ２を接着した後、
第６図に示す公知のワイＡ７ボンダ３で該半導体チップ
２の各ボンディングパッド２ａとリードフレーム１の各
リード１ｂとを金線等の細いワイヤで接続する（第６図
において、３ａは上下動するボンディングアーム、３ｂ
はボンディングヘッドすなわちキャピラリ、４はボンデ
ィングヘッド３ｂの出口において形成されたワイヤ溶融
球づなわちボールである）。[Technical Background of the Invention] When assembling a semiconductor device using a lead frame, after bonding the semiconductor chip 2 as shown in FIG. 5 onto the depth mount head 1a of the lead frame 1 as shown in FIG.
Each bonding pad 2a of the semiconductor chip 2 and each lead 1b of the lead frame 1 are connected with a thin wire such as a gold wire using a known wire A7 bonder 3 shown in FIG. bonding arm, 3b
is a bonding head or capillary, and 4 is a wire molten sphere or ball formed at the exit of the bonding head 3b).
第６図のごときワイヤボンディング工程では、従来、各
ボンディングパッド２ａに対づるボンディングアーム３
ａの上下動ストロークＳは第７図に示すように一定であ
り、ボンディングパッドの高さ位置Ａにおいてワイヤの
ボール４が潰れるようにストローク下限位置が設定され
ている。 従つ−（、各ボンディングパッド２ａに対す
るボンディングヘッドのストローク下限位置もすべて同
一高さ位置ぐあった。In the wire bonding process as shown in FIG. 6, conventionally, bonding arms 3 are attached to each bonding pad 2a.
The vertical movement stroke S of a is constant as shown in FIG. 7, and the lower limit position of the stroke is set so that the wire ball 4 is crushed at the height position A of the bonding pad. Accordingly, the stroke lower limit positions of the bonding head for each bonding pad 2a were also all located at the same height.
［背傾技術の問題点］
前記のごとき従来のワイヤボンディングｈ法において各
ボンディングパッドに対するボンディングヘッドのスト
Ｌ１−り長及びストローク下限位置を同一値に設定して
いるのは、半導体チップ２をブツブマウントヘッド１ａ
に接着しているはんだ層もしくは接着剤層等の接着層５
が該半導体チップ２の全面にわたって同じ１９ざｔであ
って半導体グツ／が水平に固るされていると仮定してい
るためぐある。 しかしながら現実には、接着層５のＥ
ｅｌ １９がゝ１′埒休′ｒ−ツブ２の全面にわたって
等しくなることは希であり、通常は第８図に示すように
、接？′Ｉ層５５の層）９は半導体デツプ２の各部にお
いてｙ＜なっ（いるため半導体チップ２は水平よりも傾
いた状態でチップマウントヘッド上に固定されている。[Problems with back-tilting technology] In the conventional wire bonding method as described above, the stroke length L1 and the stroke lower limit position of the bonding head for each bonding pad are set to the same value, because the semiconductor chip 2 is mount head 1a
Adhesive layer 5 such as a solder layer or an adhesive layer adhered to
is the same 19 times over the entire surface of the semiconductor chip 2, and it is assumed that the semiconductor chip is fixed horizontally. However, in reality, the E of the adhesive layer 5
It is rare for el 19 to be equal over the entire surface of ゝ1'傝咥'r-bulb 2, and usually, as shown in FIG. Since the layer 9 of the I layer 55 has y< (at each part of the semiconductor depth 2), the semiconductor chip 2 is fixed on the chip mount head in a state tilted from the horizontal.
従って、このような状態の半導体デツプ（こ対して従
来方法でワイヤボンダイングを行うと、ボンディングパ
ッドの高さ位置とボンディングヘツドのストローク下限
位置とが一致しイτくなり、その結果、ボンディング不
良を生じやりいという問題点があった。Therefore, if wire bonding is performed using the conventional method, the height position of the bonding pad and the lower limit position of the stroke of the bonding head will coincide with each other, resulting in a failure of bonding. There was a problem that it was difficult to get started.
このような問題点を解消するために、ボンｉ゛イングア
ームにボンディングパッド検出子をｊＱｔＪ−（おき、
ボンディングヘッド下降時に各ボンディングパッドの高
さ位置を検出するとともにその検出値に基いてボンディ
ングヘッドの下降ス］・１１−りを制御するという方法
が提案されているが、この方法では、検出信号の演算処
理の時間が極め（’Ｊａ）いため、この方法を実１ｊｌ
！ｉ？ｌるにはボンディングヘッドの下降ス１−〇−り
速度を極めて遅くしな＋ｊればならない。 従って、こ
の方法によると生産能率が著しく低下することは避けら
れない。In order to solve this problem, a bonding pad detector is placed on the bonding arm.
A method has been proposed in which the height position of each bonding pad is detected when the bonding head is lowered, and the lowering stroke of the bonding head is controlled based on the detected value. Since the calculation processing time is extremely long, this method is not practical.
! i? In order to do this, the descending speed of the bonding head must be extremely slow. Therefore, according to this method, it is inevitable that the production efficiency will be significantly reduced.
［発明の目的１
このざｔ明は前記のごとき問題を解決ｊＪるためになさ
れたもの（・あり、この発明の目的は、ボンディング不
良の発生を防止覆ることができると同時に生産能率も向
上づることができるワイヤポンプイングツ）法すなわ／
３￥導体装置の製造方法を提供づることである。[Objective of the Invention 1 This invention was made in order to solve the above-mentioned problems.The object of the invention is to prevent and eliminate the occurrence of bonding defects and at the same time improve production efficiency. Wire pump pumps that can be used)
3. To provide a method for manufacturing a conductor device.
［発明の概要］
本発明者は前記問題点を解決するために種々の試行をＩ
Ｊった結果、本発明の方法によれば生産能率の向上と同
時にボンディング不良の発生防止とが達成できることが
明らかとなった。[Summary of the Invention] The present inventor has made various attempts to solve the above problems.
As a result, it has become clear that the method of the present invention can improve production efficiency and prevent bonding defects at the same time.
本発明の方法では、ワイヤボンディングに先立つ″（半
導体チップの傾きやボンディングパッドの高さ位置等を
検出するとともにこの検出値に基いＣ各ボンディングパ
ッドに対するボンディングヘッドのストローク下限位置
及び高速下降域とを演算しておき、ワイヤボンディング
工程ではこの演ＲＩ＋１．＋に阜いてボンディングヘッ
ドを制御Ｉすることを特徴とりる。In the method of the present invention, prior to wire bonding, the tilt of the semiconductor chip, the height position of the bonding pad, etc. are detected, and based on the detected values, the lower limit stroke position and high-speed descending region of the bonding head for each bonding pad are determined. is calculated in advance, and in the wire bonding process, the bonding head is controlled based on this calculation RI+1.+.
本発明の方法によれば、従来方法よりもボンディングヘ
ッドの平均動作速度が向上して生産能率が向上Ｊるとと
もにボンディング不良の発生は著しく低下してワイヤボ
ンディングの歩留りが著しく白土することがわかった。It has been found that, according to the method of the present invention, the average operating speed of the bonding head is improved compared to the conventional method, improving production efficiency, and the occurrence of bonding defects is significantly reduced, resulting in a marked decline in wire bonding yield. .
本発明の方法では、ボンディングパッドの検出器はボン
ディングヘッドとは別イ１／置に設りられ、該検出器に
よる検出を受（〕たず導体チップのみにツイヤボンディ
ングが実施される。 ボンディングパッドの検出器は機
械式、光学式、超合彼式等のいずれの形式でもよい。In the method of the present invention, the bonding pad detector is installed in a separate location from the bonding head, and the bonding is performed only on the conductor chip without being detected by the detector. Bonding The pad detector may be of any type, such as mechanical, optical, or super-combinant.
［発明の実施例〕
第１図及び第２図に本発明方法の実施に使用りる装置の
一例を示づ。 同図に示す装置はライＮ／ボンダに附設
されるボンディングパッド検出器Ｖｌであり、半導体チ
ップ２に対して上下動するノ′−ムロと、該アーム６の
先端に設けられたプ［」−シフとを有しており、該アー
ム６はアーム作動機構８に支持され（いる。 そしてア
ーム作動機構８は駆動装置９によって駆動されるように
なっている。 アーム作動機構８には第２図に示づ」、
うにアーム６の基端部を収容する凹部が設けられ、該凹
部にはアーム６の基端部を回転可能に支持りる軸１０が
設けられている。 また、該四部内にはアーム基端部の
上面を下向きに１ｌｌ＝Ｉ勢Ｊるばね１１が設（プられ
るとともにアーム基端部の下面に係合する一ノイクロス
イッチ１２が設けられている。[Embodiment of the Invention] FIGS. 1 and 2 show an example of an apparatus used to carry out the method of the present invention. The device shown in the figure is a bonding pad detector Vl attached to the line N/bonder. The arm 6 is supported by an arm actuating mechanism 8. The arm actuating mechanism 8 is driven by a drive device 9. shown in
A recess is provided to accommodate the base end of the arm 6, and a shaft 10 for rotatably supporting the base end of the arm 6 is provided in the recess. Further, within the four parts, a spring 11 is provided which forces the upper surface of the base end of the arm downwardly, and a pressure switch 12 is provided which engages with the lower surface of the base end of the arm. .
マイクロスイッチ１２の回路はワイヤホンダの制御装置
に接続されている。 第２図に示すようにプロー７７が
ボンディングパッド面に接触していない時にはばね１１
の力によってマイクロスイッチ−１２が閉じるようにな
っており、また、第３図に示すＪ、うにプローブ７がボ
ンディングパッドに接触１Ｊるどマイクロスイッチ１２
が開かれるようになっている。The microswitch 12 circuit is connected to the Wire Honda controller. As shown in FIG. 2, when the plow 77 is not in contact with the bonding pad surface, the spring 11
The force causes the microswitch 12 to close, and the probe 7 contacts the bonding pad 1J as shown in FIG.
is about to be opened.
アーム作動機構８は駆動装置９によって昇降動され、そ
のｈ１降動の♀はワイヤボンダの制御装置に入力される
ようになっている。The arm operating mechanism 8 is moved up and down by a drive device 9, and the ♀ of the lowering h1 is inputted to the control device of the wire bonder.
本発明方法ぐは、第７図に示す装置で半導体チップ２の
各ボンディングパッドの高さ位置を以下のＪ、うにして
検出した後、該半導体チップにワイ（アボンディングを
行う。 すなわら、ボンディングパッドの畠さ検出工程
では、アーム作動機構８を上下動させてプローブ７を半
導体チップ２の四隅のボンディングパッドに接触させて
該□チップの傾きと金ボンディングパッドの高さ位置を
算出し、この算出値に基いて次のライ１フボンデイング
１程でのボンディングヘッドの下降限位置ど高速下降ス
ト［］−り長とを各ボンディングパッドｈｊｋ：演Ｃ）
し、この演韓結果に基いてワイヤボンディングを・行う
。In the method of the present invention, after the height position of each bonding pad of the semiconductor chip 2 is detected in the following manner using the apparatus shown in FIG. 7, the semiconductor chip is bonded. In the step of detecting the height of the bonding pad, the arm operating mechanism 8 is moved up and down to bring the probe 7 into contact with the bonding pads at the four corners of the semiconductor chip 2, and the inclination of the chip and the height position of the gold bonding pad are calculated. , based on this calculated value, determine the lowering limit position of the bonding head in the next life bonding 1 and the high-speed lowering stroke [] - length of each bonding pad hjk: Performance C)
Then, wire bonding is performed based on this performance result.
［発明の効果］
本発明の方法によれば、各ボンディングパッドに対する
ボンディングヘッドの下降限位置をｉｔ Ｍ（に制御で
きるのでボンディング不良の発生を未然に防止すること
ができて半導体装置の歩留りが向上（る。 また、ボン
ディングヘッドの高速ト晴ストローク長がｌ確に算出で
きるので高速上院領域に続く低速下降領域を従来よりｂ
短縮づることができ、その結果、ボンディング能率が向
上Ｊる（たとえば１００ビンの半導体チップをワイヤボ
ンディングする場合には従来方法にくらべて１チップ当
り ２秒の時間短縮が可能となった）。′なお、前記実
施例では各ボンディングパッドの高さ位置とチップの傾
きを検出するために該ヂッゾに機械的に接触するプロー
ブを使用しているが、１ツブの傾き（もしくは接着層の
厚みの偏差）やボンディングパッドの高ざイ１装置を検
出する方法として超音波方式による厚み検出や光学的厚
み検出等の１ｊ７１ ｉ ４Ｑ用しＣムよいことは勿論
であり、本発明のｊノ法が実施例のみに限定されないこ
とは当然Ｃ゛ある。[Effects of the Invention] According to the method of the present invention, the lowering limit position of the bonding head for each bonding pad can be controlled to it M(, thereby preventing the occurrence of bonding defects and improving the yield of semiconductor devices. (In addition, since the high-speed downward stroke length of the bonding head can be accurately calculated, the low-speed downward region following the high-speed upper region can be
As a result, bonding efficiency is improved (for example, when wire bonding 100 bins of semiconductor chips, the time can be reduced by 2 seconds per chip compared to the conventional method). 'In the above embodiment, a probe that mechanically contacts the bonding pad is used to detect the height position of each bonding pad and the tilt of the chip. It goes without saying that ultrasonic thickness detection, optical thickness detection, etc. can be used as a method for detecting bonding pad height (deviation) and bonding pad height. Of course, it is not limited to only the examples.
第１図は本発明方法の実施に用いる検出装置の一例を示
−ｔ ｌ１ｔＫ略図、第２図は第１図の一部の拡大図、
第３図は第１図の装置の一状態を示Ｊ拡人図、第４図【
まリードフレームの平面図、第５図はり一ドル−ムのデ
ツプマウントヘッド上に接着された４′導体チップの平
面図、第６図はワイヤボンディング上程の概略図、第７
図はワイヤボンディング上程に３３けるず脚体チップと
ワイヤホンダのボンディングヘッドとの関係を説明する
ための説明図、第Ｅ３図は２Ｖ導体チップが傾いて固定
されている状態を小した図である。
１・・・リードル−ｌい、 １ａ・・・チップマウン
トヘッド、 １ｂ・・・リード、 ２・・・＋導体
１ツブ、２ａ・・・ボンディングパッド、 ３・・・ワ
イへ７ボンダ、３ａ・・・ボンディングアーム、 ３ｂ
・・・ボンディングヘッド、 ４・・・（ワイヤの）ボ
ール、 ５・・・接着層、 ６・・・アーム、 ７・・
・プローブ、 ８・・・アーム作動機構、 ９・・・駆
動装置、 １０・・・軸、１１・・・ばね、 １２・・
・マイク［Ｊスイッチ。
第１図
第４図
第５図
第６図FIG. 1 is a schematic diagram showing an example of a detection device used for carrying out the method of the present invention, and FIG. 2 is an enlarged view of a part of FIG. 1.
Figure 3 shows one state of the device in Figure 1.
Fig. 5 is a plan view of the lead frame; Fig. 5 is a plan view of the 4' conductor chip bonded on the one-drum depth mount head; Fig. 6 is a schematic diagram of the wire bonding process; Fig. 7 is a plan view of the lead frame;
The figure is an explanatory diagram to explain the relationship between the 33-piece chip and Wire Honda's bonding head in the upper stage of wire bonding, and Figure E3 is a miniature diagram of the state in which the 2V conductor chip is tilted and fixed. . 1...Leadle-l, 1a...Chip mount head, 1b...Lead, 2...+1 conductor tab, 2a...Bonding pad, 3...Wide 7 bonder, 3a...・・Bonding arm, 3b
...bonding head, 4... (wire) ball, 5... adhesive layer, 6... arm, 7...
・Probe, 8... Arm actuation mechanism, 9... Drive device, 10... Axis, 11... Spring, 12...
・Microphone [J switch. Figure 1 Figure 4 Figure 5 Figure 6
Claims (1)
るに先立つて該半導体チップの各ボンディングパッドの
高さ位置を検出する検出工程を設け、該検出工程におい
て検出された該半導体チップの傾き及び各ボンディング
パッドの高さ位置等のデータに基いて各ボンディングパ
ッドに対するボンディングヘッドのストロークと高速下
降域とを算出しておき、ワイヤボンディング工程におい
てはその算出値に従って各ボンディングパッド毎にボン
ディングヘッドを制御してワイヤボンディングを行うこ
とを特徴とする半導体装置の製造方法。1. Prior to performing wire bonding on a semiconductor chip, a detection step is provided to detect the height position of each bonding pad of the semiconductor chip, and the inclination of the semiconductor chip and the height of each bonding pad detected in the detection step are The stroke and high-speed descending range of the bonding head for each bonding pad are calculated based on data such as height position, and in the wire bonding process, the bonding head is controlled for each bonding pad according to the calculated values to perform wire bonding. A method for manufacturing a semiconductor device, characterized by performing the following steps.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59140598A JPS6120342A (en) | 1984-07-09 | 1984-07-09 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59140598A JPS6120342A (en) | 1984-07-09 | 1984-07-09 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6120342A true JPS6120342A (en) | 1986-01-29 |
Family
ID=15272419
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59140598A Pending JPS6120342A (en) | 1984-07-09 | 1984-07-09 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6120342A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7598205B2 (en) | 2005-02-18 | 2009-10-06 | Toyota Jidosha Kabushiki Kaisha | Exhaust gas purifying catalyst |
| US7737078B2 (en) | 2004-12-03 | 2010-06-15 | Toyota Jidosha Kabushiki Kaisha | Catalyst for purifying exhaust gas |
-
1984
- 1984-07-09 JP JP59140598A patent/JPS6120342A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7737078B2 (en) | 2004-12-03 | 2010-06-15 | Toyota Jidosha Kabushiki Kaisha | Catalyst for purifying exhaust gas |
| US7598205B2 (en) | 2005-02-18 | 2009-10-06 | Toyota Jidosha Kabushiki Kaisha | Exhaust gas purifying catalyst |
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