JPS6171657A - Laser trimming method - Google Patents

Laser trimming method

Info

Publication number
JPS6171657A
JPS6171657A JP59194107A JP19410784A JPS6171657A JP S6171657 A JPS6171657 A JP S6171657A JP 59194107 A JP59194107 A JP 59194107A JP 19410784 A JP19410784 A JP 19410784A JP S6171657 A JPS6171657 A JP S6171657A
Authority
JP
Japan
Prior art keywords
package
laser beams
hybrid
trimming
laser beam
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59194107A
Other languages
Japanese (ja)
Inventor
Toshio Komiyama
込山　利男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP59194107A priority Critical patent/JPS6171657A/en
Publication of JPS6171657A publication Critical patent/JPS6171657A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Apparatuses And Processes For Manufacturing Resistors (AREA)

Abstract

PURPOSE:To prevent damage from being generated by measurement probes by a method wherein a hybrid IC sealed in a package is processed with laser beams from outside the package. CONSTITUTION:The hybrid IC6 is internally bonded to outer leads 4 with Au wires 7 and the like, and further processed with laser beams 5 so as to come into required functions while being measured with the outer leads 4 of the IC package 1 resulting from outer sealing with an impermeable insulating resin 2 which is impermeable to laser beams 5 and a permeable insulating resin 3 which is permeable to laser beams 5. This manner enables functional trimming with laser beams 5 while the IC is measured with the outer leads 4 of the final IC package 1 resulting from outer sealing; therefore, defects such as damage due to element trimming and characteristic changes due to outer sealing can be eliminated.

Description

【発明の詳細な説明】 （技術分野） 本発明はレーザ光線が透過できる透過窓を自するＩＣパ
ッケージに封止された混成集積回路のレーザトリミング
方法に関するものである。TECHNICAL FIELD The present invention relates to a method for laser trimming a hybrid integrated circuit sealed in an IC package having a transmission window through which a laser beam can pass.

（従来技術） 従来混成染積回路ではセラミック、ガラエボ基板等の表
ｒｎＪに薄膜または厚膜技術てよシ受動素子として抵抗
やコンデンサを１設け、きらに前記受動素子が所定の値
になるよう測定グローブ等の測定針で各受動素子を測定
しなからレーザ光線により素子トリミングを行う。凍た
、組立技術（マウント、ボンディング寺）により能動素
子としてＩＣペレット等の接続および外部リードを取付
けた後、所定の回路Ｆ！＆能になるよう外部リード端子
で測定１−なからレーザ光線により総合ｆＡ臀として機
能トリコンブを行い、さらに外装刺止をし混５′ｉ、染
槓回路装［なとしていた。(Prior art) In conventional hybrid dyed circuits, one resistor or capacitor is provided as a passive element using thin film or thick film technology on the front surface of a ceramic or Gala Evo board, and then the passive element is measured to a predetermined value. Each passive element is measured with a measuring needle such as a glove, and then the element is trimmed with a laser beam. After freezing and assembling technology (mounting, bonding) to connect IC pellets as active elements and attach external leads, the predetermined circuit F! Measurements were made using the external lead terminals to make it possible to perform 1-function trichome with a laser beam as a general fA buttock, and then the exterior was pierced, mixed, and dyed.

よって、素子トリミングのときの測定グローブによるキ
ズ不良や外装封止におけろＳＴ止材料および上止時の筒
温処理による時性変化等の欠点があった０ （発明の目的） 本発明の目的は屁成梨槓回鮎を外装封止された外部から
レーザ光線により所定の惨能になるようにするレーザト
リミング力法およびＩＣパッケージについて提供するも
のである。Therefore, there were disadvantages such as scratches caused by the measuring glove during element trimming, and temporal changes due to the ST sealing material during exterior sealing and cylinder temperature treatment during top sealing. provides a laser trimming force method and an IC package in which a predetermined damage is achieved by using a laser beam from the outside of a sealed pear.

（発明の構成） 本発明は混１１１Ｍ集株回路をＩｃパッケージに外装刺
止し、…」記混成集株回路をＩＣパッケージの外部リー
ドより測定しながら所定の機能になるようレーザ光線に
て機能トリミングをすることを特徴とする。(Structure of the Invention) The present invention consists of attaching a mixed 111M integrated circuit to the exterior of an IC package, and measuring the hybrid integrated circuit from the external lead of the IC package using a laser beam to achieve a predetermined function. It is characterized by trimming.

（失施七タリ） 以下図面を用いて詳細に説明をする。(Shishitari) A detailed explanation will be given below using the drawings.

第１図は本発明による一゛実施例で混成集権回路をＩＣ
パッケージ１に外装封止した図を示したものである。ま
た第２図は前記第１図のＡ−Ａ’断面図およびレーザ光
線５でレーザ・トリミングを実施している状態を示した
もので、外部リード４に混成実値回路６をＡｕワイヤー
７等で内部接合し、ざらにレーザ光′＃Ａ５が透過でき
ない不透過性樹脂樹脂２およびレーザ光線５が透過でき
る透過ｅｅｈ、を樹脂３により外装封止したＩＣパ、ケ
ージｌの外部リード４で測定しながら所定の機能になる
ようレーザ光線５で加工することができる。FIG. 1 shows one embodiment of the present invention in which a hybrid centralized circuit is integrated into an IC.
This figure shows a package 1 that is externally sealed. FIG. 2 is a cross-sectional view taken along the line A-A' in FIG. The opaque resin resin 2, through which the laser beam '#A5 cannot pass through, and the transmission eeh, through which the laser beam 5 can pass through, are measured using the external leads 4 of the IC package and cage l, which are internally bonded with and sealed with resin 3. However, it can be processed with the laser beam 5 so as to have a predetermined function.

（発明の効果） 本発明によれば所定の混成集積回路機能にするために外
装封止した最終ＩＣパッケージ１の外部リード４で測定
しなからレーザ光線５で機能トリミンクができるため、
従来の素子トリミングによるキズ不良および外装封止に
よる特性変化等の欠点を解決することができる他、非ｎ
ｉＣ筒棺韮の混成集権回路も可能となる。また従来の検
査用オートハンドラーを使用しながら機能トリミングが
できるため生産ラインの自動化も容易となる０なお本発
明の外装樹脂は全てレーザ光＄５が透過する透過性樹脂
３でも良いことはもちろんである０(Effects of the Invention) According to the present invention, functions can be trimmed using the laser beam 5 without measuring the external leads 4 of the final IC package 1 which is sealed in order to achieve a predetermined hybrid integrated circuit function.
In addition to solving the drawbacks of conventional device trimming such as scratches and characteristic changes due to external sealing, it is possible to
It also becomes possible to create a hybrid integrated circuit using an iC tube. In addition, since functional trimming can be performed while using a conventional inspection autohandler, it is easy to automate the production line.It goes without saying that the exterior resin of the present invention may all be a transparent resin 3 through which laser light passes through. Some 0

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明による混成集積回路用ＩＣバ。 ケージの斜視図の一実施例で、第２図は第１図に示した
ＩＣパッケージのＡ−Ａ’断面においてレーザ光線で加
工している断面図を示す。 ｌ・・・・・ＩＣパッケージ、２・・・・・・不透過性
樹脂、３・・・・・透過性樹脂、４・・・・・外部リー
ド、５・・・・・・レーザ光線、６・・・・・・混成集
権回路、７・・・・・・Ａｕワイヤー。FIG. 1 shows an IC bar for a hybrid integrated circuit according to the present invention. FIG. 2 is an embodiment of a perspective view of a cage, and FIG. 2 shows a cross-sectional view of the IC package shown in FIG. 1 taken along the line AA' and processed with a laser beam. l...IC package, 2...opaque resin, 3...transparent resin, 4...external lead, 5...laser beam, 6... Hybrid centralized circuit, 7... Au wire.

Claims (1)

【特許請求の範囲】[Claims] （１）パッケージに封止された混成集積回路を、前記パ
ッケージの外部からレーザ光線により加工することを特
徴とするレーザトリミング方法。(1) A laser trimming method characterized in that a hybrid integrated circuit sealed in a package is processed with a laser beam from outside the package.
JP59194107A 1984-09-17 1984-09-17 Laser trimming method Pending JPS6171657A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59194107A JPS6171657A (en) 1984-09-17 1984-09-17 Laser trimming method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59194107A JPS6171657A (en) 1984-09-17 1984-09-17 Laser trimming method

Publications (1)

Publication Number Publication Date
JPS6171657A true JPS6171657A (en) 1986-04-12

Family

ID=16319046

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59194107A Pending JPS6171657A (en) 1984-09-17 1984-09-17 Laser trimming method

Country Status (1)

Country Link
JP (1) JPS6171657A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1069618A4 (en) * 1998-04-01 2001-08-22 Ricoh Kk Semiconductor device and manufacture thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1069618A4 (en) * 1998-04-01 2001-08-22 Ricoh Kk Semiconductor device and manufacture thereof

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