JPS6171649A - Ic package - Google Patents
Ic packageInfo
- Publication number
- JPS6171649A JPS6171649A JP59194309A JP19430984A JPS6171649A JP S6171649 A JPS6171649 A JP S6171649A JP 59194309 A JP59194309 A JP 59194309A JP 19430984 A JP19430984 A JP 19430984A JP S6171649 A JPS6171649 A JP S6171649A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- hall
- lead frame
- coated
- resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3135—Double encapsulation or coating and encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、ＩＣチップを封止する際、ＩＣチップに歪
を与えない構造のＩＣパッケージに関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an IC package having a structure that does not apply distortion to an IC chip when the IC chip is sealed.
〔従来の技術
従来のＸＣパッケージの断面構造図を第２図に示す。Ｉ
Ｃチップ１はダイアタッチ材８により、リードフレーム
６に接着されている。さらに半導体基板上のパッドとリ
ードフレームとは金属ワイヤ７により電気的に接続され
ており、これら全体を外気から遮断するモールド材５と
から構成されている。[Prior Art] A cross-sectional structural diagram of a conventional XC package is shown in FIG. I
The C chip 1 is bonded to the lead frame 6 using a die attach material 8. Further, the pads on the semiconductor substrate and the lead frame are electrically connected by metal wires 7, and are comprised of a molding material 5 that isolates the entirety from the outside air.
しかし、このような従来のパッケージではシリコン基板
のような圧電物質を用いた半導体基板を実装する場合、
次のような不具合を生じるっ第１にリードフレーム２と
ＩＣチップ１との熱膨張係数の差からダイアタッチ材８
を介してＩＣチップに歪を与える。第２にＩＣチップ１
をモールド材料５により封止すると、モールド材料５と
ＩＣチップ１の熱膨張係数の差によりＩＣチップは表面
及び側面から歪をうける。ＩＣチップ上にホール素子の
ような磁気変換素子を集積化する禍−合ホール素子の出
力端子間に磁場によるホール電圧を検出するのであるが
、前述のパッケージからＩＣチップが受ける歪のために
圧電効果によりホール電圧出力端子間にオフセット電圧
を生じ、チンプ状想から比較して特性を変えてしまう。However, with such conventional packages, when mounting a semiconductor substrate using piezoelectric material such as a silicon substrate,
The following problems occur: First, due to the difference in thermal expansion coefficient between the lead frame 2 and the IC chip 1, the die attach material 8
applies distortion to the IC chip through the Second, IC chip 1
When the IC chip is sealed with the molding material 5, the IC chip is subjected to distortion from the surface and side surfaces due to the difference in thermal expansion coefficient between the molding material 5 and the IC chip 1. When a magnetic transducer such as a Hall element is integrated on an IC chip, the Hall voltage due to the magnetic field is detected between the output terminals of the Hall element, but due to the strain that the IC chip receives from the package mentioned above, piezoelectric This effect causes an offset voltage between the Hall voltage output terminals, changing the characteristics compared to the chimp state.
−例としてリードフレーム６にリン青銅を用いダイアタ
ッチ材８に銀ペーストを用い、シリコンチップをエポキ
シｍ１ｌＷで封止した場合のホールＩＣの磁気オフセッ
トの温度特性の変動を第６図に示す。第５図かられかる
ように一４０℃から＋７０℃の間で２００ガウスもの変
動を生じる。ホールエＣの要求特性としては磁気オフセ
ットは２００〜２５０ガウス以内でなければならず、上
述のような歪による大幅な磁気オフセット変動は除去し
なければならない。- As an example, FIG. 6 shows the variation in the temperature characteristics of the magnetic offset of a Hall IC when phosphor bronze is used for the lead frame 6, silver paste is used for the die attach material 8, and the silicon chip is sealed with epoxy mlW. As can be seen from Figure 5, a fluctuation of as much as 200 Gauss occurs between -40°C and +70°C. The required characteristics of Hall-E-C are that the magnetic offset must be within 200 to 250 Gauss, and the large magnetic offset fluctuations due to distortion as described above must be eliminated.
そこで、この発明はホールＩＣのようにパック３−ジか
ら受ける歪により特性が変動してしまうＩＣチップの実
装においてＩＣチップに歪を与えてしまうという従来の
欠点を除去したＩＣパッケージを提供するものである。SUMMARY OF THE INVENTION Therefore, the present invention provides an IC package that eliminates the conventional drawback of giving distortion to an IC chip when mounting an IC chip, such as a Hall IC, whose characteristics vary due to distortion received from a pack. It is.
上記問題点を解決するために、この発明はＩＣチップを
フレキシブル基板にリードを介して取り付はＩＣチップ
をシリコーン樹脂で被覆し、さらにそのまわシをモール
ド樹脂で被覆した構成とし、ホールエ０に対する応力を
低減した。In order to solve the above problems, the present invention has a structure in which the IC chip is mounted on a flexible substrate via a lead, the IC chip is coated with silicone resin, and the cover is further covered with mold resin, and the hole evaporator is covered with mold resin. Reduced stress.
上記のように構成されたＩＣパッケージを用いると、温
度が変動する場合、ＩＣチップのまわりのシリコーン樹
脂の硬度が小さいため、モールド樹脂の熱膨張によるＩ
Ｃチップへの応力を小さくでき、磁気オフセットの変動
を小さくできる。または、ＩＣチップがフレキシブル基
板のリードを介してパッドのみで接合しているため、７
レキシプル基板からの応力の影響を小さくでき、磁気オ
フセットの変動を小さくできる。When using an IC package configured as described above, when the temperature fluctuates, the hardness of the silicone resin around the IC chip is small, so the thermal expansion of the molding resin causes an I.
The stress on the C chip can be reduced, and the fluctuations in magnetic offset can be reduced. Or, because the IC chip is connected only with pads via the leads of the flexible board, 7
The influence of stress from the lexical board can be reduced, and fluctuations in magnetic offset can be reduced.
以下にこの発明の実施例を図面にもとづいて詳細に説明
する。Embodiments of the present invention will be described in detail below based on the drawings.
第１図においやリードフレーム３はフレキシブル基板２
にバンブ接合などにより、電気的に導通且つ固着されて
いる。ＩＣチップは前記リードフレーム２の先端に接合
されている。このホールＩＣ１のまわりをシリコーン樹
脂４で被覆し、そのシリコーン樹脂４で被われたＩＣチ
ップをモールド材５で被覆している。このよりにＩＣチ
ップをフレキシブル基板２に付け、シリコーン樹脂４で
被蔭した場合はＩＣチップに対する応力を解放できるの
で磁気オフセントを小さくできる。このｔＡ合の磁気オ
フセットの温度特性を第４図に示す。Fig. 1 The lead frame 3 is the flexible substrate 2
They are electrically connected and fixed by bump bonding or the like. The IC chip is bonded to the tip of the lead frame 2. The Hall IC 1 is covered with a silicone resin 4, and the IC chip covered with the silicone resin 4 is covered with a molding material 5. As a result, when the IC chip is attached to the flexible substrate 2 and covered with the silicone resin 4, the stress on the IC chip can be released, so that the magnetic offset can be reduced. FIG. 4 shows the temperature characteristics of the magnetic offset at this time tA.
この場合、ＩＣチップは全くモールドに歪を受けず、−
４０℃から＋８０℃の間の磁気オフセット変動はＩＣチ
ップ固有の温度特性を持つだけとなるっ
〔発明の効果〕
この発明は以上説明したようにｒｅテップのパンケージ
ングによる応力を小さく抑えるものであり、シリコンの
ようよ圧電物質を用いたホール素子の実装ひずみ及び磁
気オフセントの温度特性の低減に大きな効果がある。In this case, the IC chip is not distorted by the mold at all, and -
Magnetic offset fluctuations between 40°C and +80°C only have temperature characteristics specific to the IC chip. [Effects of the Invention] As explained above, this invention suppresses the stress caused by re-step pancaging to a small level. This has a great effect on reducing the temperature characteristics of mounting distortion and magnetic offset of Hall elements using piezoelectric materials such as silicon.
第１図は、この発明に係るホールＩＣパッケージの断面
図、第２図は従来のホールＩＣパッケージの断面図、第
５図は従来のホールＩＣパッケージの磁気オフセントの
温度特性図、第４図は本発明のホールＩＣパッケージの
磁気オフセットの温度特性図である。
１・・・・・・・・・工０チップ
２・・・・・・・・・フレキシブル基板３・・・・・・
・・・リード
４・・・・・・・・・シリコーン樹脂
５・・・・・・・・・モールド樹脂
６・・・・・・・・・リードフレーム
７・・・・・・・・・ワイヤ
以 上
出願人 セイコー電子工業株式会社
代理人 弁理士 最 上 務
６１ノートフレーム
第；３図
一痴
第４図
台−FIG. 1 is a sectional view of a Hall IC package according to the present invention, FIG. 2 is a sectional view of a conventional Hall IC package, FIG. 5 is a temperature characteristic diagram of magnetic offset of a conventional Hall IC package, and FIG. FIG. 3 is a temperature characteristic diagram of magnetic offset of the Hall IC package of the present invention. 1...... Process 0 Chip 2... Flexible board 3...
...Lead 4...Silicone resin 5...Mold resin 6...Lead frame 7... Wire and above Applicant Seiko Electronic Industries Co., Ltd. Agent Patent Attorney Mogami 61 Note Frame No. 3 Figure 1 Chi Figure 4 Table -
Claims (1)
接続されたリードフレームと、該リードフレームと接続
されたフレキシブル基板と、前記ＩＣチップの周囲を被
覆するシリコーン樹脂と、前記シリコーン樹脂を被覆す
る樹脂モールドとから成るＩＣパッケージ。A lead frame electrically connected to pads on an IC chip via metal bumps, a flexible substrate connected to the lead frame, a silicone resin covering the periphery of the IC chip, and a silicone resin covering the IC chip. An IC package consisting of a resin mold.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59194309A JPS6171649A (en) | 1984-09-17 | 1984-09-17 | Ic package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59194309A JPS6171649A (en) | 1984-09-17 | 1984-09-17 | Ic package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6171649A true JPS6171649A (en) | 1986-04-12 |
Family
ID=16322460
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59194309A Pending JPS6171649A (en) | 1984-09-17 | 1984-09-17 | Ic package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6171649A (en) |
Cited By (22)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63310141A (en) * | 1987-06-11 | 1988-12-19 | Nec Corp | Semiconductor device |
| US5989940A (en) * | 1994-05-26 | 1999-11-23 | Nec Corporation | Semiconductor device capable of accomplishing a high moisture proof |
| US6781359B2 (en) | 2002-09-20 | 2004-08-24 | Allegro Microsystems, Inc. | Integrated current sensor |
| US6995315B2 (en) | 2003-08-26 | 2006-02-07 | Allegro Microsystems, Inc. | Current sensor |
| US7075287B1 (en) | 2003-08-26 | 2006-07-11 | Allegro Microsystems, Inc. | Current sensor |
| US7166807B2 (en) | 2003-08-26 | 2007-01-23 | Allegro Microsystems, Inc. | Current sensor |
| US7476816B2 (en) | 2003-08-26 | 2009-01-13 | Allegro Microsystems, Inc. | Current sensor |
| US7598601B2 (en) | 2003-08-26 | 2009-10-06 | Allegro Microsystems, Inc. | Current sensor |
| US7709754B2 (en) | 2003-08-26 | 2010-05-04 | Allegro Microsystems, Inc. | Current sensor |
| US8080994B2 (en) | 2006-05-12 | 2011-12-20 | Allegro Microsystems, Inc. | Integrated current sensor |
| JP2013069809A (en) * | 2011-09-21 | 2013-04-18 | Toyota Motor Corp | Semiconductor device |
| JP2014027266A (en) * | 2012-06-20 | 2014-02-06 | Asahi Kasei Electronics Co Ltd | Semiconductor package and manufacturing method of the same |
| US8907437B2 (en) | 2011-07-22 | 2014-12-09 | Allegro Microsystems, Llc | Reinforced isolation for current sensor with magnetic field transducer |
| US9190606B2 (en) | 2013-03-15 | 2015-11-17 | Allegro Micosystems, LLC | Packaging for an electronic device |
| US9620705B2 (en) | 2012-01-16 | 2017-04-11 | Allegro Microsystems, Llc | Methods and apparatus for magnetic sensor having non-conductive die paddle |
| US9666788B2 (en) | 2012-03-20 | 2017-05-30 | Allegro Microsystems, Llc | Integrated circuit package having a split lead frame |
| US9812588B2 (en) | 2012-03-20 | 2017-11-07 | Allegro Microsystems, Llc | Magnetic field sensor integrated circuit with integral ferromagnetic material |
| US10234513B2 (en) | 2012-03-20 | 2019-03-19 | Allegro Microsystems, Llc | Magnetic field sensor integrated circuit with integral ferromagnetic material |
| US10345343B2 (en) | 2013-03-15 | 2019-07-09 | Allegro Microsystems, Llc | Current sensor isolation |
| US11644485B2 (en) | 2021-10-07 | 2023-05-09 | Allegro Microsystems, Llc | Current sensor integrated circuits |
| US11768230B1 (en) | 2022-03-30 | 2023-09-26 | Allegro Microsystems, Llc | Current sensor integrated circuit with a dual gauge lead frame |
| US11800813B2 (en) | 2020-05-29 | 2023-10-24 | Allegro Microsystems, Llc | High isolation current sensor |
-
1984
- 1984-09-17 JP JP59194309A patent/JPS6171649A/en active Pending
Cited By (32)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63310141A (en) * | 1987-06-11 | 1988-12-19 | Nec Corp | Semiconductor device |
| US5989940A (en) * | 1994-05-26 | 1999-11-23 | Nec Corporation | Semiconductor device capable of accomplishing a high moisture proof |
| US7265531B2 (en) * | 2002-09-20 | 2007-09-04 | Allegro Microsystems, Inc. | Integrated current sensor |
| US6781359B2 (en) | 2002-09-20 | 2004-08-24 | Allegro Microsystems, Inc. | Integrated current sensor |
| US6995315B2 (en) | 2003-08-26 | 2006-02-07 | Allegro Microsystems, Inc. | Current sensor |
| US7166807B2 (en) | 2003-08-26 | 2007-01-23 | Allegro Microsystems, Inc. | Current sensor |
| US7075287B1 (en) | 2003-08-26 | 2006-07-11 | Allegro Microsystems, Inc. | Current sensor |
| US7476816B2 (en) | 2003-08-26 | 2009-01-13 | Allegro Microsystems, Inc. | Current sensor |
| US7598601B2 (en) | 2003-08-26 | 2009-10-06 | Allegro Microsystems, Inc. | Current sensor |
| US7709754B2 (en) | 2003-08-26 | 2010-05-04 | Allegro Microsystems, Inc. | Current sensor |
| US8080994B2 (en) | 2006-05-12 | 2011-12-20 | Allegro Microsystems, Inc. | Integrated current sensor |
| US8907437B2 (en) | 2011-07-22 | 2014-12-09 | Allegro Microsystems, Llc | Reinforced isolation for current sensor with magnetic field transducer |
| JP2013069809A (en) * | 2011-09-21 | 2013-04-18 | Toyota Motor Corp | Semiconductor device |
| US10333055B2 (en) | 2012-01-16 | 2019-06-25 | Allegro Microsystems, Llc | Methods for magnetic sensor having non-conductive die paddle |
| US9620705B2 (en) | 2012-01-16 | 2017-04-11 | Allegro Microsystems, Llc | Methods and apparatus for magnetic sensor having non-conductive die paddle |
| US9666788B2 (en) | 2012-03-20 | 2017-05-30 | Allegro Microsystems, Llc | Integrated circuit package having a split lead frame |
| US10916665B2 (en) | 2012-03-20 | 2021-02-09 | Allegro Microsystems, Llc | Magnetic field sensor integrated circuit with an integrated coil |
| US9812588B2 (en) | 2012-03-20 | 2017-11-07 | Allegro Microsystems, Llc | Magnetic field sensor integrated circuit with integral ferromagnetic material |
| US11961920B2 (en) | 2012-03-20 | 2024-04-16 | Allegro Microsystems, Llc | Integrated circuit package with magnet having a channel |
| US10230006B2 (en) | 2012-03-20 | 2019-03-12 | Allegro Microsystems, Llc | Magnetic field sensor integrated circuit with an electromagnetic suppressor |
| US10234513B2 (en) | 2012-03-20 | 2019-03-19 | Allegro Microsystems, Llc | Magnetic field sensor integrated circuit with integral ferromagnetic material |
| US11828819B2 (en) | 2012-03-20 | 2023-11-28 | Allegro Microsystems, Llc | Magnetic field sensor integrated circuit with integral ferromagnetic material |
| US11677032B2 (en) | 2012-03-20 | 2023-06-13 | Allegro Microsystems, Llc | Sensor integrated circuit with integrated coil and element in central region of mold material |
| US11444209B2 (en) | 2012-03-20 | 2022-09-13 | Allegro Microsystems, Llc | Magnetic field sensor integrated circuit with an integrated coil enclosed with a semiconductor die by a mold material |
| JP2014027266A (en) * | 2012-06-20 | 2014-02-06 | Asahi Kasei Electronics Co Ltd | Semiconductor package and manufacturing method of the same |
| US9190606B2 (en) | 2013-03-15 | 2015-11-17 | Allegro Micosystems, LLC | Packaging for an electronic device |
| US10753963B2 (en) | 2013-03-15 | 2020-08-25 | Allegro Microsystems, Llc | Current sensor isolation |
| US10345343B2 (en) | 2013-03-15 | 2019-07-09 | Allegro Microsystems, Llc | Current sensor isolation |
| US9865807B2 (en) | 2013-03-15 | 2018-01-09 | Allegro Microsystems, Llc | Packaging for an electronic device |
| US11800813B2 (en) | 2020-05-29 | 2023-10-24 | Allegro Microsystems, Llc | High isolation current sensor |
| US11644485B2 (en) | 2021-10-07 | 2023-05-09 | Allegro Microsystems, Llc | Current sensor integrated circuits |
| US11768230B1 (en) | 2022-03-30 | 2023-09-26 | Allegro Microsystems, Llc | Current sensor integrated circuit with a dual gauge lead frame |
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