JPS616837A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To easily execute dynamic bias test by comprising a shift clock generating circuit and a shift-in data producing circuit. CONSTITUTION:For the dynamic bias test, operations of the shift clock generating circuit 1 and the shift-in data producing circuit 2 are started by setting an input of BT terminal 30 to ''1'', an output of the shift clock generating circuit 1 is supplied to the flip-flops 51-54 through the NAND gates 12, 13, an output of the shift-in data producing circuit 2 is supplied to the input of shift-in of the flip-flop 51 through the NAND gates 21, 23, and the shift operations of flip-flops 51-54 are started by making ''1'' an output of the OR gate 41. In this case, the other circuits of the main circuit 5 start the operations simultaneously. Operations of the circuit do not have any meaning, in this case, but it is sufficient for satisfying the object of dynamic bias test.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a semiconductor integrated circuit incorporating a dynamic bias test circuit.

(Prior Art) Semiconductor integrated circuits (hereinafter referred to as ICs) are subjected to bias tests to ensure their reliability.

Conventional bias testing involves applying a 10% higher power supply voltage, fixing the input to t"o" or 1", and placing the device in a high-temperature furnace for tens to hundreds of hours. Therefore, especially complementary semiconductor integrated circuits (hereinafter referred to as C
It's called MO8IC. ), due to its circuit characteristics, almost no current flows in the circuit when the human input signal does not fluctuate, and a normal bias test was insufficient as a load test. Therefore, especially in the case of CMOSICs, tests that vary the input signal during bias testing (
Hereinafter, this is called a dynamic bias test. ), but the external circuit for varying the input signal had many problems, as described below, and required an expensive circuit.

1) Since the number of input signals and terminal positions differ depending on the type of IC under test, a dedicated mounting board is required for each type.

2) To supply a large number of external signals into the high temperature furnace,
A large number of wiring is required, and the electrical components used must be able to withstand high temperatures for long periods of time.

:3) A large space is required for mounting external circuits.

(Object of the Invention) An object of the present invention is to provide a semiconductor integrated circuit that can easily perform a dynamic bias test by solving the above-mentioned problems.

(Structure of the Invention) Clock generation means for internally supplying a shift clock according to the bias test command, and data that generates shift ino data according to the dynamic bias test command and supplies it to the input of the shift bus circuit. and generating means.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

This embodiment consists of a shift clock generation circuit 1, a BT terminal 30 to which a dynamic bias test command is input, and a CLK terminal 10 to which a normal shift clock is input.
and a NAND gate 1 that selectively switches between the signal from the CLK terminal 10 and the signal from the shift clock generation circuit 1.
1, 12.13, the shift-in data generation circuit, the SIN terminal 20 which inputs the shift-in data during normal operation, the signal from the SIN terminal 2o, and the signal from the shift-in data generation circuit 2. NAND to select and switch signals
The main circuit 5 includes gates 21, 22, 23, an SFT terminal 40 for inputting a shift operation command, and flip-flops 51, 52, 53, and 54 forming a shift bus. In addition, 31 is an inverter,
41 is an OR gate.

In this embodiment, normally, the BT terminal 300 Å voltage is set to 0'', the output of the inverter 31 becomes '1'', and a shift clock is received from the CLK terminal 10 via the NAND gate 11, and the NAND gate 22 is via SIN terminal 20
It is ready to receive shift-in data from
A shift operation is performed when the SFT terminal 40 becomes 1''.

When performing a dynamic bias test, BT
By setting the input to the terminal 30 to 1'', the operation of the shift clock generation circuit 1 and the 7ft-in data generation circuit 2 is started, and the output of the shift clock generation circuit 1 is sent through the NAND gates 12 and 13. The output of the shift-in data generation circuit 2 is supplied to the flip-flops 51 to 54 through the NAND gates 21 and 23.
Shift operations of flip-wrap flops 51 to 54 are started. Generally, in a synchronous logic circuit, the peripheral circuits also operate together with the movement of the clip clock, and in this embodiment, most of the circuits in the main circuit 5 are connected to the flip-flops 51 to 54. They are supposed to move together. Therefore, as shown above, the clip flop 5
When the circuits 1 to 54 start the shift operation, the other circuits in the main circuit 5 also start operating together. Although the circuit operation at this time has no logical meaning, it is a dynamic circuit.
This is sufficient for the purpose of bias testing.

FIG. 2 (al is a circuit diagram showing an example of the shift clock generation circuit 1 in FIG. 1. This circuit is an oscillation circuit in which odd-numbered stages of signal inverting gates are connected in a loop. The purpose of the resistor is to reduce the oscillation period appropriately.Second
The timing diagram in Figure (b) shows the movements of points A, B, and C in the circuit. Output C is connected to NAND gate 12 of FIG.

FIG. 3 is a circuit diagram showing an example of the shift I/data generation circuit 2 of FIG. 1. In the same figure, 7fir is just lLntLIi^hT^? 1Jrl J-'
The LSU inverters 25 and 26 are connected in a loop to form an oscillation circuit. The purpose of the resistance between the gates is to moderately reduce the excavation cycle. The output of gate 26 is connected to exclusive OR gate 27. A plurality of arbitrarily selected signals that are considered to operate appropriately during the shift operation within the main circuit 5 are input to the other inputs of the exclusive logic 0 gate 27. These are circuits whose purpose is to generate moderately random data as shift ino data, and have no other special meaning.

As explained above, according to this embodiment, 0MO8IC
Dynamic bias testing can be easily performed without the problems of preparing a special board as in the past.

Incidentally, since the purpose of the present invention is to appropriately perform 111 operations in the main circuit 5 during a bias test, the shift clock generation circuit 1. The shift-in data generation circuit 2 does not need to be very precise, and a circuit similar to that of this embodiment is sufficient, but other suitable circuits may be used depending on the case.

(Effects of the Invention) As described above in detail, the semiconductor integrated circuit of the present invention incorporates a shift clock generation circuit and a shift-in data generation circuit, thereby easily performing a dynamic bias test. It has the effect that it can be carried out.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 (
al and (b) are a circuit diagram and its timing diagram showing an example of the shift clock generation circuit in Fig. 1, and Fig. 3, respectively.
FIG. 1 is a circuit diagram showing an example of the shift ino data generation circuit shown in FIG. l...Shift clock generation circuit, 2...
・Shift-in data generation circuit, 5... Main circuit, 10... CLK terminal, 11, 12.13.
...NAND gate, 20...SIN terminal, 21, 22, 23゜24...NAND gate, 25.26...Inverter, 27...
...Exclusive OR gate, 30...BT terminal, 31...Inverter, 40...SF
T terminal, 41...OII'-T, 50...
...Shift bus input signal lines, 51-54...Flip/70 rings. Agent: Patent Attorney Shinkyo Uchihara 1 time

Claims (1)

[Claims] In a semiconductor integrated circuit having a shift bus circuit, there is provided a clock generating means for internally supplying a shift clock according to a dynamic bias test command, and a clock generating means for generating shift-in data according to the dynamic bias test command, - A semiconductor integrated circuit characterized by comprising: data generation means for supplying data to an input of a bus circuit.