JPS6166973A - Automatic testing system using timing generator, performancethereof is improved - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention]

TECHNICAL FIELD OF THE INVENTION The present invention relates to automatic testing systems, and more particularly to automatic test systems that utilize timing generators to provide timing signals to electronic devices or circuits under test. Automated testing methods are conventionally known. FIG. 1 is a block diagram of a typical conventional automated testing scheme 10. The test method 10 includes a master clock 11, a vector sequence operation logic 12, a device under test (1) UT) power supply 13
, parameter measurement unit I-(1) MtJ) 14,
Central processing unit (CI'tJ) 15, computer memory] 6, local peripheral device 17, communication interface 1
8 and a user workstation 19. Master clock 11 is a mask system clock and supplies a master clock (i) which is normally generated from a very stable element such as a quartz crystal. I) The tJT power supply 13 supplies the desired voltage and voltage to the device under test DtJT 30 under CPU control. PMtJI4 serves to supply the current level.
I) Utilized to measure selected electrical parameters of D U +30 under U control. CP tJ
15 controls the overall operation of the test system 1110. It is used as a stage for storing data used by the computer memory l611tCP II15. Local peripheral device 17 is typically a peripheral device d such as a line printer, video display, etc. A communication interface 18 allows the test system 10 to communicate with other systems/, if desired.
It is +11 ability to provide it to make it 1 ability. Knee + J
The workstation 19 is used by a user to access the system 10 for testing the device at 4/J, for monitoring the test results, for running a specific test), etc. It is provided to make it possible to control the operation of the 2I computer bus 201
115, computer memory 16, local peripherals 17, communications interface 18, user workstation 19, and additional computers or peripherals (not shown). 1110 has a limited number of timing generators 24, each of which provides a single analog timing signal whose leading and trailing edges are controlled by CP tJ ],5. In traditional test systems, timing generators are expensive and therefore limited in number, and in early automated systems, the devices to be tested were relatively small and compared to today's device, and therefore only a relatively small number (i.e., about 16) of timing generators were needed to perform all the electrical tests of the device under test. Rather, a complex switching matrix 25 can be used to essentially act as a cross-point switch, since the timing signals provided by a limited number of timing generators can be used on any lead of the device under test. The operation allows signals from a limited number of timing generators to be applied to selected ones of the waveform formatters 26. This also
It allows a single timing signal to be applied to multiple ports of DUT 30 in multiple formats during a single test period. As the complexity of electrical devices increases,
0-1- As the number of nodes increases, the switch sigma 1~
The risk 25 must be even larger and more complex, and therefore more expensive. A waveform formatter 26 receives timing signals from a limited number of timing generators 24 and supplies the appropriate test waveforms to the pin electronics 27. Some of these test waveforms are shown in FIG. 2a. Although it is possible for those skilled in the art to use other such waveforms as shown in FIG. Baku 1~
During these timing periods, the logic 0, 0,
0. ], l, 0. All transitions are reflected on one or more edges of the timing generator. 2nd a
The remainder of the figure shows the result of combining the timing generator information and the test data information to create a non-return-to-zero (NRZ) true data signal where the edge is turned off at the beginning of each timing generator clock period. , edge provides NRZ false data, return zero (R'l"Z) true data, return rawan (RT○) false data, and RTZ false data that appear at the beginning of each timing generator clock period. The test system IO also backs up. 1 hell memory 22. Vector memory 22 stores a plurality of test vectors, each essentially defining a binary signal applied to D tJ T 30 and its The test vector consists of a plurality of bits that define the appropriate output signals to be received by the device under test to function properly in response to the input signals defined by the word.
The memory 22 connects multiple devices 1 to the tester data bus 23.
- CI to supply vectors sequentially) UI 5 controls the vector memory 22. Switching matrix 2 to supply analog signals to pin electronics 27 which supply analog test signals to DUT30.
5 by a limited number of timing generators 24! These test vectors are received by waveform formatter 26 in response to the test vectors provided by vector memory 22 and timing signals. Waveform formatter 26 (FIG. 1) is controlled by CPtJ]5 via tester access bus 21 to select the appropriate NAT waveform for each of the devices 30 under test. Although only six such waveform formatters are shown in FIG.
A waveform formatter is included for each lead of the device inside. These are often of the order of 60 to 120 -1, thus providing a 60 to 120 waveform formatter. The output signal from waveform formatter 26 is applied to a suitable one of pin electronics 27. Again, a plurality of pin electronics circuits are provided, one such pin electronics circuit for each lead of the device under test that can be controlled simultaneously by the computer test system 10. . Pin electronics 27 combines the analog signal from waveform formatter 26 and the voltage and current provided by DUT supply 13 to
Provide appropriate test signals to the U T 30. Many factors are important when testing electronic devices. First, the ability to apply accurate selection voltages and currents is essential. Second, the ability to determine current and voltage levels as a result of test operations is important. Third, accurate timing of test signals applied to or measured from the device under test is essential. For example, RAM, ROM
, FROM, etc., appropriate address signals are applied to the device under test, and the device under test provides an output word that identifies the exact address to be stored in the memory device. It is compared to a table of data. Naturally, all memory devices require a certain amount of access time, so the tester must read the output word from the device under test before reading the output word from the device under test to determine whether the output word from the device under test is 1F or not. It must wait for a period of time after applying the address signal. The first condition is that sufficient timing voltage and current sources must be available to interrogate all pins of the device under test for each test cycle. However, as integrated circuit devices become more complex, a limited number of timing generators may become insufficient, making it possible to test all pins with a limited number of timing generators. required for complex configurations. Therefore, the test system must be able to provide very accurate timing information to the device under test and accurately measure time as the information is returned by the device under test. Additionally, manufacturers specify and customers require that such devices operate at certain speeds. In other words, for the example memory device, it is expected that the user can expect to receive the appropriate data on the output leads of the memory device within a period of time after applying the address signal. Therefore, when testing such devices, it is fundamental that the output signal is received within a specific time after supplying the address signal to the device under test. Therefore, the test system 10 must be capable of providing timing information to the device under test with great accuracy and accurately measuring time as the information is returned by the device under test. Therefore,
Once the timing generator 24 supplies timing signals to the vector memory 22 under the control of the central processing bag [15], these timing signals are as accurately as possible D t
It is necessary to reach the appropriate lead of J T 30. However, as in any system, there is a propagation delay between timing generator 24 and DUT 30. Furthermore, these propagation delays will vary depending on the exact path the timing signal must take from timing generator 24 to the appropriate destination of DUT 30. In other words, each waveform formatter 26 has its own specific propagation delay. Second, each pin electronics 27
also has its own specific propagation delay. Thirdly,
The switching matrix 25 is connected to the timing generator 24
An additional unequal propagation delay is provided to each timing M that is lumillized from the waveform formatter 26 to the waveform formatter 26. If the timing signal of IIL- is routed to the leads of multiple waveform formatters and thus l) tJ T 30, the timing signal routes its route to the various leads of LJT 30! - different propagation delays are encountered at -. Each propagation delay provided by switching matrix 25, waveform formatter 26, and pin electronics 27 is cumulative in nature, so that each timing signal is transferred from timing generator 24 to I) tJ i'
30 is delayed by its own propagation delay. Once arriving at the device under test 30, each of these propagation delays must be adjusted to be as equal as possible in order to maintain the relative timing of the timing signals. Therefore, within each path between timing generator 24 and DtJT3Q there are a number of so-called "deskew"
elements are provided. Such correction elements 31 are located in selected paths of the switching matrix 25, in selected ones of the waveform formatters 26, and in the pin electronics 2.
7, each path in the switching matrix 25, each waveform formatter 26
, it should be understood that each pin electronics 27 can have its own correction element 31 for maximum accuracy. The correction element 31 includes an additional adjustable element 3 such that the total propagation delay along each path from the timing generator 24 to the device under test 30 can be made equal.
Supply 1. It is possible to use manual or computer-controlled correction elements. The manual correction element 31 is
It usually has an RC delay circuit and is usually manually adjusted. In other words, during the manufacture of computer test system 10 and subsequent repair and maintenance operations, it is expensive to measure the propagation delay between timing generator 24 and device under test 30. It is necessary that the test equipment be used by a skilled technician. These engineers then perform these corrections 11. Equipment; 31
1111 of the timing generator 24 and the D IJ T30 by manually adjusting all or some of the
The propagation delays of the two must be made as close as possible. However, this is a fairly time-consuming task, requiring skilled technicians and expensive measuring equipment. As history has often found, such adjustments are often made to improve timing generator 24 and device under test 30.
must ensure that the propagation delay between In addition to being quite expensive, such reconditioning necessarily renders the computerized test system 10 unusable, causing undesirable downtime and thus reducing the production of the computerized test system 10. resulting in loss of capacity. Also, as the complexity of the timing path increases,
It becomes more difficult to equalize the propagation delays imparted by all paths. At the same time, customers are demanding faster and more complex devices to be tested with increased accuracy. Modern correctional elements use digital-to-analog converters that convert analog values in response to a digital word that controls the switching threshold voltage level of the gate! In doing so, it provides an adjustable gate propagation delay. Although this simplifies the engineer's work, the problem of having a complex signal path requiring correction i1E remains. Such correction elements are rather complex, expensive and not completely accurate. In addition to the fact that the propagation delays between timing generator 24 and DUT 30 are different and must be adjusted, it has further been discovered that the propagation delays provided by waveform formatter 26 are depends on whether the data provided by the vector memory 22 controlling the vector memory 22 is a logic 1 or a logic O. Since this type of correction in propagation delay depends on the test data, corrections that depend on such data are conventionally difficult or extremely difficult, and approximate correction
Therefore, it can be seen that the errors occurring within the timing 4g supplied to the device under test 330 are generated by several sources. 1. Errors in the centrally generated timing signal detected by the timing generator 24. These errors are due to resolution limitations of timing generator 24 and calibration errors. 2.1 ~ Riff 1 ~ and errors in the switching matrix 25 due to crosstalk. 3. Limits of resolution, 1-to riff 1, correction element: 11-element due to measurement error occurring during adjustment of 31;
Error within 31. 4. Error in waveform formatter 26. 5. I) due to differences in voltage swings identified in the device under test 30 TI']'': 30
Changes in the rise time of issue 411. 6. Drift 1~, Cross]~-, an error in the master clock 11 caused by a calibration error. Having these multiple sources of error in conventional systems is itself a problem. Since timing information is exposed to each of these errors sequentially as we proceed from the timing generator 26 to the DUT 30, a typical unified H1 analysis shows that the overall error is the sum of the individual errors. It is. Even when all elements of the timing path are constructed with the best technology, the overall error is the sum of these individual errors and is therefore much larger than if there were a smaller number of error sources. An error exists. Another major problem associated with the adjustment correction elements 31 contained within the switching matrix 25 is that the switching matrix 25 is used to connect the timing generator 24 to the various waveform formatters 26 during operation of the test system 10. is constantly being reorganized. Due to this switching of the 71 helix 25, the propagation path and thus the propagation delay through the switching matrix 25 constantly changes. This means that the correction elements provided in the switching matrix 25 in order to eliminate the uniform correction flattening provided by the switching matrix 25 can only be adjusted approximately. However, in practice, the selected path through the switching matrix 25 typically has a propagation delay that is either greater or less than the uniform propagation delay through this switching matrix 25; Therefore, the correction +E element 31 present in the switching matrix 25 is only able to correct the switching matrix 25 approximately. The present invention has been made in view of the following points, and -1
- The aim is to overcome the drawbacks of the prior art as mentioned above and to provide unique automatic test data in which timing signals are generated in a novel manner compared to conventional test methods. According to the invention, all adjustments to the propagation delay of the timing signal are made digitally by adjusting digital information that defines when the analog timing signal 411 is generated. In this way, propagation delay correction occurs automatically under computer control and does not require careful adjustment of hardware correction elements. Furthermore, by digitally adjusting the propagation distortion, it is possible to correct the propagation distortion depending on the data value (logic O and logic 1). Furthermore, according to the invention, the timing signal is provided by three timing edges rather than by timing pulses, thereby making the generation of the timing signal more accurate. Another feature of the invention is that it eliminates the use of complex switching matrices by providing at least one timing generator per pin of the device under test; It eliminates propagation errors associated with
The present invention provides additional capabilities and simplifies the problems associated with creating software used to control a test system during testing of a device under test at the same time. Hereinafter, specific embodiments of the present invention will be described in detail with reference to the accompanying drawings. In accordance with the present invention, a unique test scheme with multiple functions is provided, including: (1) providing a timing generator assigned to each of the devices under test; (2) Since no timing generator is shared among many pins of the device under test, switching (3) All timing compensation is done with one timing value and one timing generator, reducing the number of error terms.
(4) It is possible to increase the timing by edges rather than pulses, thus making it possible to use more than two edges to form a waveform. One embodiment of a test scheme constructed in accordance with the present invention is shown in block diagram form in FIG. Test I method 10 is
Master clock 111, DUT power supply 113, PMUI
14. CPUI 1.5. computer memory 116;
Local peripheral device 117, communication interface 118
, user workstation 119, etc., which are found in any automated testing scheme. Therefore, these elements are well known to those skilled in the art, and detailed description thereof is omitted herein. Furthermore, the test method 10 uses an ECL tester controller 11.
2, which has the function of assisting the tester CPU 115 in controlling the test hardware,
Also, a vector memory 1 containing a plurality of test vectors.
It has 22. Testing scheme 100 further includes a waveform formatter 23, which combines the test vector data to describe a selected waveform for each pin of the device under test during each test cycle. Importantly, test scheme 100 includes a plurality of timing generators 124, typically about 16 in number.
0, but can be any desired number. Many conventional test systems strive to minimize the number of timing generators used to minimize cost. One such conventional system outputs the output from the selected timing generator to the selected lead of one or more of the devices in 5 tests.
Significant efforts have been made to provide switching matrices for selectively connecting g.g. Such conventional schemes also require significant effort and expense to correct errors in propagation delays provided by such matrices. In contrast to the prior art, the present invention performs the test scheme R1 from a different perspective. In contrast to the conventional one-way test method, the test method constructed according to the present invention uses a plurality of timing generators 124.
each timing generator is individually associated with a specific Pinelectronics unit,
The pin electronics units 1 to 1 are D tJ T 30
It is related to the individual ratio of -1. That is, instead of designing each timing generator to be used in multiple boards of D[J T30 via a complex switching matrix, the present invention effectively reduces the use of each timing generator to Limited to LJ T 30 individual leads. This is contrary to the concept of conventional test methods, because the test method constructed based on the present invention is capable of testing devices with a large number of leads. This is because it requires a larger number of timing generators than what was originally needed. However, the present invention provides several unique advantages. First, it uses more timing generators, but the additional timing generators give programmers and users more flexibility in testing the device. Second, each timing generator is individually associated with a specific pin electronics circuit, so
The need for a switching matrix is eliminated, thus providing cost savings. More importantly, eliminating the switch sigma 1-lix eliminates the propagation delays and distortions between propagation delays that are caused by using the switch sigma 1-lix. Therefore, fewer correction elements are required, calibration is significantly relaxed, and accuracy is improved. Also, by having a timing generator for each pin, it is possible to sequentially reverse the waveform formatting function and the timing function, so that the waveform formatting is a digital selection, from which a timing signal is generated and further processed. used without hesitation. By using Timing No. 1 without further processing, we reduce the number of error sources and improve the accuracy of the timing signal. We also format the waveform before generating the timing signal. This configuration allows for the use of different timing information for logic 1 and logic O data, adding a new element of timing accuracy that was previously impossible. By removing the complex switch sigma 1~risk, it is possible to treat timing edges independently instead of pulses, making it possible to use more than 1 or 2 edges, and the The result is the ability to create more complex waveforms as desired by the user. The test method 100 further includes a digital waveform formatter 123, which is very difficult and expensive to make practical.
This is different from the conventional analog waveform formatter 26 shown in FIG. In response to test vectors provided by vector memory 122 via vector bus 122a, digital waveform formatter 123 provides digital output words on bus 123a to timing generator 124. The digital words provided by digital waveform formatter 123 are derived in response to vectors provided by vector memory 122. Each vector stored in vector memory 122 has two 29 parts, as shown in FIG. In one embodiment of the invention, each vector stored in vector memory 122 has three
2+N bit words, where N is the number of pins on DUT 30. The first 10 bits of the 32-bit portion of the test vector form the global cycle type (OCT). The global cycle type is D[JT130
is common to each timing generator 124 (FIG. 3) associated with each lead. The global cycle type should be tested by this test vector 1H.I) TJT
One set of 128 possible waveforms for each of the 130 leads is identified. Although a large number of possible waveforms can be generated by test scheme 100,
It is almost certain that a relatively small number of these waveforms will be used during any given sequence of test steps during the 130 tests. Therefore, the user can specify this set of waveforms before running a test sequence to test OUT'130. O
CT helps determine which silk waveform to use with this particular test vector. In other words, instead of trying to decide which of a number of possible test waveforms to apply to each lead of the DtJT 130, the 10-bit OCT determines which set of these waveforms to use during this test step. Help you decide what to do. In this way, the relatively small 10-bit OCT addresses the global-to-local cycle table 150, which functions as a look-up table that further determines which of a number of possible waveforms for each pin the DUT 130 of this set of waveforms. to each lead. OCT also determines the duration of the waveform to be generated by the test vector. Of course, the OCT can be made to have more than 10 bits, or not be used at all if desired. Also, as shown in Figure 4, each 32-bit field of the test vector includes 6 bits that define the mask (M) word, 6 bits that define the drive (D) word, and 6 bits that define the inverse (I) word. DtJT 30 for each test cycle, which collectively serves as another method for controlling which waveform in waveform table 150 is selected for each pin of DtJT 30 for each test cycle. This different selection ability consists of compatibility with the traditional eggplant one-way system! It is set up for the purpose of learning. The information to the remaining N pinots 1 in the test vector 122a is
data and a single bit associated with each read of the DtJT 130, where N is the total number of reads of the IJT]30. This data is a logical value, i.e. a logical 0 or a logical 1.
is applied to each waveform selected by each global-to-local cycle table 150 for this cycle. The OCT, M, D words are applied as addresses to the tally pull-to-local cycle table 150. The selected global-to-local cycle table 150 value, vector data value, and I word value are each 1) LJ
It is used to select the entry i in the waveform table 151 associated with the T lead. An important feature of the present invention is that all waveform and data information is treated as digital information for selecting entries in the waveform table, and the waveform information is not applied to the timing pulse information as in conventional schemes. . More importantly, vector data values allow one of several different wave table values to be selected depending on this data value, with timing can be adjusted independently, a capability that has not been possible with conventional methods. Since many desired waveforms can be defined by at least three edges, test scheme 100 constructed in accordance with the present invention uses three separate edge generators 124-1 to 30 per DUT lead. 1.24-3. Of course, it will be apparent to those skilled in the art that the present invention may be applied with more or less than three edge generators per pin. In fact, it is possible to use a single edge generator in conjunction with a device under test and to configure the edge generator to provide more than one edge per test cycle. Referring again to FIG. 4b, each edge generator 124-]
There are 64 separate sets of waveform information stored in the waveform table 15. The entries selected from waveform table 51 provide information that configures the timing generator for each test cycle. In one embodiment of the invention, a waveform table entry consists of 72 bits, which are comprised of three independent timing edge generators 24-1 through 12.
4-3. These 24 bits are used to select which waveform circuit type to use, which of the 1024 master clock cycles to trigger the timing edge generator, and which 100 ps step The edge generator at 1. after the trigger cycle. OO picoseconds to 5
9. Select whether to operate over a range of 9 seconds. Another important feature of the invention is that in one embodiment, three separate gamma edge generators are provided for each pin. For this reason, each edge is processed by an independent circuit, rather than by the same circuit as in the conventional system where the timing is treated as a pulse with two edges of 1ll-. This allows for timing resolution of 100 picoseconds over a complete 1°024 master clock counter 1-Iil with no gaps or put zones. If timing is treated as pulse information and formatting information is applied to the timing pulse after it is formed, it is very difficult to avoid dead zones in timing, and in fact many traditional test methods I have a zone. In other words, the propagation delay for an analog signal to transition from logic O to logic 1 is:
Even though the analog signals travel along exactly the same path through test scheme 100, the propagation delay of the analog signal's logic 1 to logic O transition is different. Conventional systems were not capable of correcting for this propagation delay difference along a sub-path due to the state of the data being transmitted along that path. However, according to the present invention, two separate words are selected from the waveform table 15 and used for each edge generator, one of which is associated with the logical O data, and the other of which is associated with the logic O data. It is related to logic 1 theta.Therefore,
The propagation delay along each path is considered separately for logic O and logic 1 information, providing a significant improvement in accuracy compared to the conventional one-way approach. Another important feature of the invention is that per pin: 3-) γ
The timing edge! The advantage of this is that it provides more timing information than the conventional test model using two edge pulses. All this without the Suinotingma helix.]
This is achieved as a direct result of having one timing generator dedicated to each of the L pins. In particular, in one embodiment. The seven circuit types selected are drive high, drive paper, drive off, strobe off (pedance), strobe high, and strobe off. The present invention provides an arrangement based on complementary true data (driving paper, driving height, driving paper), and an encircling based on complementary false data (driving height, driving paper).
drive paper, drive height), generalized I10 switch and strobe stem (drive off, strobe height, strobe off)
, and the generalized I10 switch and strobe false (drive off, strobe low, strobe off) complex waveforms (illustrated in Figure 2b) can be formed,
This was not possible with traditional test methods without multiple switching matrices. The operation of one embodiment of the test method constructed according to the present invention will be described with reference to FIGS. 3, 4a, and 4b. First, at periodic intervals (e.g., once a month), the computerized test system 100 is run through an automatic calibration unit ("Autocall J").
13] automatically by using Caliplay I.
- That is, calibrate. When the test method 100 is set to the auto call mode, the CPU] 15 is set to the auto call unit 3
The foot 131 controls the timing edge for each pin electronics unit 127 sequentially for each of the seven edge types: 1-) for each time delay stored in the calibration table shown in FIG. 4a. occurs. Therefore, in the embodiment shown in FIG. 4a, the calibration table has an identical sub-table for each pin in the pin electronics unit 1-27. Each sub-table of the calibration table forms a matrix, which is determined by the computer test system 100 at what times the edge is applied to the associated pin electronics unit. Store digital information that defines what should be generated. As shown in FIG. 4a, in this embodiment of the invention, each sub-table of the calibration table provides a matrix defined by each of seven edge types, and ranges from 0 to 59.0 in 100 ps increments. Ij a specific time period within the range of 9 nanoseconds
, Eru. Although only times within the range of 0 to 59.9 nanoseconds are stored in the calibration table of this embodiment, the information stored in the waveform table 151 is not received from the calibration table. generates a wide range of time types because it has a part that determines how many master clock counts of a high-precision master clock must be performed before using the time delay specified by the data It is possible. For example, if a 100 nanosecond delay is desired, 8 master clock counts of the precision 12 nanosecond clock are performed before forming a 4 nanosecond delay as specified in waveform table 151 (i.e., 96 nanoseconds). nanoseconds), and at that time, a 100 nanosecond delay is given to generate this edge. A calibration table range greater than 12 nanoseconds is used to allow timing edges to move freely across test cycle boundaries without creating any timing dead zones. Importantly, since the master clock count is performed with a high precision clock (i.e., within 0.5.ip),
Ignore any minor count timing errors i)
(ie, less than 20 picoseconds), no adjustment can be made for timing errors due to the minor callan. Thus, in accordance with the present invention, a periodic computer test [~system A]00 is automatically entered into a gear replacement table at a specified time increment at the beginning of a timing period. store digital information defining when to operate each edge generator associated with each of the I) U l' + 30 bins to supply a physical timing edge to the bin elect [1 nic unino] 1-; . When converted, the 11 bits associated with a specific edge type and specific delay time are stored in the calibration table.

[. The digital data generated changes the actual timing of each edge to eliminate timing errors caused by any source. Each sub-table of the key A replacement table has a system offseller 1 for each edge type. This system Offsera 1 ~ is Pin Ellen 1 ~ Ronix 127 and DUTI 3
Define the actual analog distortion located between the 0 and associated leads. This analog distortion is caused by differences in propagation delays between the pin electronics 127 and the associated leads of the DtJT 130, and along the path of the load boat containing the desocket that holds the DUT 130 during electrical testing. These system offsets are user-determined hardware-dependent, such as the load board and the circuitry configured within it, so system offsets may vary if the load board is changed. This system offset calibration is extremely easy to perform, takes little time, and is a useful calibration method to ensure that highly accurate timing edges are provided to each lead of the DUT 130. This analog delay calibration is, as is known in the art,
It can be implemented by any suitable technique, and therefore, detailed description thereof will be omitted. Therefore, the appropriate system offset value associated with the particular waveform type stored in the calibration table and the particular waveform type stored in the calibration table is:
A desired time delay is added to generate the waveform edge in the system 11 that looks up digital information associated with the waveform type to be used and in doing so compensates for analog distortion within the system 11. Importantly, in accordance with the present invention, all timing and analog distortions within system 11 are compensated for by modifying the programmed digital values of the timing generator edges. This reduces the number of sources of timing errors to a minimum and [1] adds the timing error terms generated at several points in the system constructed according to the present invention and 11-) analog timing pulses. Unlike conventional systems, which must compensate for these errors by adjusting the timing information, the present invention allows for greater accuracy by adjusting the digital timing information. A single test vector is used at any given time while the vector memory 122 cycles through the test vectors that define the test sequence to be applied to the UT 130. As previously mentioned, the first 10 bits of the test vector define the global cycle type, which defines the timing period and addresses one global-to-local cycle table 150 (FIG. 41), which in turn defines the timing period for each pin electronics unit 127. and thus each lead of the DUT 130 is to be selected from the waveform table 150. Accordingly, the OCT addresses words in the global-to-local cycle table 150, which accesses words stored in the waveform table 150, which extracts a single waveform from multiple waveforms stored in the waveform table 150. Define when and what types of edges should be generated for the cycle. Then, D.U.
For each lead of the TI 30, the waveform defined for it by the waveform table 150 consists of digital information whose timing is with any calibration adjustments determined by the calibration process. causes the type and timing of the selected waveform in the timing generator to be set. Importantly, specific pin electronics units (and therefore I
) Each waveform table associated with a particular lead of the IJT 130 consists of three parts, one for each pin electric unit], 27-1 and the three edge generators 124 associated with it. -1 to 124-3, to store data used to control each of them. Each section associated with a particular edge generator is further subdivided into two sections, one for logic O data and one for logic 1 data. Each of these portions of waveform table 151 stores a plurality of 64 individual words, thus allowing 64 possible waveforms to be selected for each back-to-back cycle. Vector memory 122
Also, as mentioned above, the test vector from M, l)
, has an I word. The test vector from vector memory 122 also has data bits, one data bit associated with each lead of DUT 130;
At that time, the logic state (ie, logic O or logic 1) of each lead of DUT 130 is determined. This data information is used by each edge generator 124-] to ]-24-3 by selecting an appropriate portion of the waveform table 151 for each edge generator 1, 2/l-] to 124-3. The precise positioning of these edges provided by edge generators 124-1 through 124-3 is determined by the data provided on each lead of DUT 130. (i.e., logic O or logic 1), then edge generator 124-1
24-3 to generate edges as accurately as possible. This ability to read and use separate information to generate edges depending on the data level of each lead means that each edge can be generated without considering the specific state of the data associated with a particular lead. This contrasts sharply with conventional test systems that were previously used. Referring to FIG. 5, each edge generator]24-1 to +
24-3 provides a plurality of output signals that control a plurality of pin electronic circuit functions that collectively provide sufficient waveform control to form a number of highly desirable waveforms. Edge generator 1 provides a drive data high signal that sets the pin electronics drive function to its logic one voltage level, a drive low logic signal that sets the pin electronics drive function to its logic low level, and turns off the pin electronics drive function. Generator + that sets the disable signal and the PinEllen1~ronics drive function to its logic high level.
24-2 as an output signal and enable the pin electronics voltage comparison function to
Step 1 to test for logic high voltage generated by T
~ Lobe high and D t with pin electronics voltage comparison function enabled. Strobe low and pin electronics voltage comparison function enabled to test for a logic low voltage generated by J T.
strobe 2 which tests the high impedance condition generated by JT. Similarly, edge generator 13 provides an output signal drive low which sets the bin electronics drive function to its logic low level and a strobe off which turns off the pin electronics strobe function. Although I-1 specific embodiments of the present invention have been described in detail below, the present invention should not be limited only to these specific examples, and without departing from the technical scope of the present invention. Of course, various modifications are possible.

[Brief explanation of the drawing]

Figure 1 is a block diagram of a conventional automatic test system, Figure 2 is a block diagram of a conventional automatic test system.
FIG. 2b is a graphical representation of a timing signal that may be provided by a structure constructed in accordance with the present invention; FIG. a block diagram of one embodiment of the structure;
FIG. 411 is a chart showing the calibration table of the system 11 in FIG. 3, and FIG.
Block diagram of H3, timing generator 124, bin electronics 127 and device under test 130, fifth
The figure is a schematic diagram of one embodiment of the pin electronics [27] of FIG. (Explanation of symbols) 100: Des 1 system 111: Master clock] 13: I') [JT power supply 1] 4: PMU +15: CPTJ 116: Combi coater memory] 17: Local peripheral device 118 2 communication interface

Claims (1)

[Claims] 1. In an automatic test method for electrically testing a device under test having a plurality of leads, a central processing unit, a vector memory for storing a plurality of test vectors, and an electrical a plurality of pin electronics units, each individually associated with one of said leads of said device under test for providing a specific test signal, each individually associated with one of said pin electronics units; a plurality of timing generators, the timing generators providing timing signals for controlling the pin electronics unit in response to data provided by the vector memory. method. 2. As defined in claim 1, each of which is individually associated with one of said timing generators and receives data from said vector memory and supplies data to said one of said timing generators. a plurality of waveform formatters for a test period, the data defining when one or more waveforms are to be generated relative to the beginning of a test period. 3. The method of claim 2, wherein one or more of the waveforms are generated by three or more timing edges controlled by the waveform formatter. 4. In claim 2, the waveform edge is applied to the pin electronics unit at a desired time after the start of the test period, relative to the start of the test period. A method characterized in that it comprises a calibration table storing information defining when waveform edges are generated by the timing generator. 5. As claimed in claim 4, said calibration tables each being individually associated with one of said timing generators in which waveform edges are generated to improve the accuracy of the test scheme. A method comprising using the information to correct for a plurality of waveform edge types and a plurality of time delays after the start of a test period. 6. In claim 5, the plurality of waveform edge types are selected from a group of waveform edge types consisting of high drive, low drive, drive off, high strobe, low strobe, strobe high impedance, and strobe off. 1. A method characterized in that it has one or more waveform edge types. 7. In claim 4, the calibration table is configured to ensure that the waveform edge is applied to the leads of the device under test at a desired time after the start of the test period. , comprising additional information defining when said waveform edge is to be generated by said timing generator, relative to the start of a test period. 8. According to claim 7, said additional information defines an analog delay provided between each said timing generator and its associated lead of said device under test. method. 9. The system of claim 1, wherein each timing generator is capable of providing three waveform edges. 10. In claim 2, each waveform formatter is capable of providing data to its associated timing generator, the data being transmitted to the device under test associated with its associated timing generator. dependent on the binary state desired on the leads of the invention. 11. An automatic test method for electrically testing a device under test having at least one lead, the method comprising a central processing unit, a vector memory for storing a plurality of test vectors, and an electrical test signal to the lead. a pin electronics unit associated with the leads of the device under test to provide a timing generator associated with the pin electronics unit; an automatic test method for testing a device under test, the method comprising: responsively providing a timing signal for control of the pin electronics unit; providing a test vector from the vector memory defining a waveform to be applied to the leads of the device under test that includes the locations of edges of the waveform; providing a digital word to the timing generator that defines a desired position of the edge of the waveform and an error generated by all sources; A method characterized in that the timing generator generates the timing signal. 12. In claim 11, in the step of providing the digital word, the digital A method characterized by adjusting words. 13. In claim 12, the step of providing the digital word comprises applying the digital word to compensate for timing errors that depend on the logic state of a waveform applied to the leads of the device under test. A method characterized by adjusting. 14. The method of claim 12, wherein the method eliminates the need for a hardware correction element.