CN116087579A - High-precision program-controlled digital time sequence waveform generating device - Google Patents

High-precision program-controlled digital time sequence waveform generating device Download PDF

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CN116087579A
CN116087579A CN202310386559.1A CN202310386559A CN116087579A CN 116087579 A CN116087579 A CN 116087579A CN 202310386559 A CN202310386559 A CN 202310386559A CN 116087579 A CN116087579 A CN 116087579A
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edge
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delay
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CN116087579B (en
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毛国梁
李全任
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Nanjing Hongtai Semiconductor Technology Co ltd
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Nanjing Hongtai Semiconductor Technology Co ltd
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/28—Provision in measuring instruments for reference values, e.g. standard voltage, standard waveform
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
    • Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Abstract

The invention discloses a high-precision program-controlled digital time sequence waveform generating device, which comprises a test processor and more than two channel time sequence generators, wherein the inlet wire ends of the channel time sequence generators are respectively connected with the test processor, the outlet wire ends of the channel time sequence generators are connected with electronic pin chips, and the channel time sequence generators comprise edge generators, waveform generators, test result generators and time recorders.

Description

High-precision program-controlled digital time sequence waveform generating device
Technical Field
The invention relates to a high-precision program-controlled digital time sequence waveform generating device, and belongs to the technical field of automatic testing of integrated circuits.
Background
Since during integrated circuit testing, an integrated circuit automatic test equipment (Auto Test Equipment, ATE) needs to provide digital stimulus signals with arbitrary timing requirements for a device under test (Device Under Test, DUT), for example: data, clock, control, etc. The periods, edges, duty cycles, etc. of various signals need to occur in real time and be precisely synchronized according to the pattern test (pattern) requirements.
In the first conventional design method, direct digital waveform synthesis (Direct Digital Frequency Synthesis, abbreviated as DDS) is realized by a high-frequency master clock, and each waveform edge occurs, including: periodic edges, waveform edges, etc. The excitation waveforms are output by respective edge synthesis. The method has low cost and good synchronism. But the edge resolution is limited by the master clock and cannot be very high. Typically in ns-order, but actual testing requires the ability to be in ps-order.
Disclosure of Invention
The invention aims to: in order to overcome the defects in the prior art, the invention provides the high-precision program-controlled digital time sequence waveform generating device, which enables ATE to be based on pattern test (pattern), not only can realize a high-precision, high-resolution and high-stability time delay chain, but also can realize real-time delay adjustment and waveform format synthesis, and simultaneously realize delay calibration according to channels, thereby realizing the generation of complex digital time sequence waveforms and the test of large-scale digital logic devices.
The technical scheme is as follows: in order to achieve the above purpose, the invention adopts the following technical scheme:
the utility model provides a high accuracy program control digital time sequence waveform generation device, includes test processor, the passageway time sequence generator more than two, passageway time sequence generator's inlet wire end is connected with test processor respectively, passageway time sequence generator's play line end all is connected with the electronic pin chip, passageway time sequence generator includes border generator, waveform generator, test result generator, time recorder, wherein:
the test processor is used for controlling and synchronizing the channel timing generator of each channel.
The edge generator is used for generating a period and generating an edge of a data waveform.
The waveform generator is used for generating designated data output waveform control signals through various edge combinations according to the waveform format and is used for generating actual physical waveforms by the electronic pin chip.
The test result generator is used for generating a comparison result with expected data according to a comparison signal returned by the electronic pin chip to form a Fail signal for the test processor.
The time recorder is used for recording time and data history information of the tested signal.
The electronic pin chip is used for generating an output signal conforming to the ViH/ViL level standard according to a control signal generated by the WFG, or converting a comparison result of VoH/VoL and the input signal into CmpH/CmpL for processing by the test result generator.
Preferably: the channel time sequence generator is a 6-channel time sequence generation module.
Preferably: the 6-channel time sequence generation module comprises 6 channel edge generators, a periodic edge generator, a driving waveform generator, a test result generator, a time measurement unit and a history record memory.
The cycle edge generator is configured to generate each cycle edge, and each cycle edge is called an initial time t0_edge of one cycle.
The driving waveform generator selectively outputs driving control waveform signals for controlling the electronic pin chip according to the edges and the waveform formats.
The test result generator is used for generating a test result Fail_Out according to the input CMP_H/CMP_ L, C0/C1 Edge of the electronic pin chip and related signals.
The time measurement unit is used for carrying out real-time information acquisition and measurement on the CMP_H/CMP_L.
The history record memory is used for recording information of each period test process in real time.
Preferably: the channel edge generator comprises an accurate edge data generator, a coarse delay edge generator, a delay chain output selector and a delay chain unit, wherein:
the precise edge data generator is used for precisely delaying the coarse delay edge to generate the input data of the delay chain output selector.
The coarse delay edge generator is configured to generate a coarse delay edge that differs from the final edge by a fine delay time.
The delay chain output selector is used for finishing the accurate delay of the coarse delay.
The delay chain unit is used for generating a delay value.
Preferably: the delay chain output selector is used for completing the accurate delay of the coarse delay, and the occurrence time of the last edge is compared with the occurrence time after T0, and is determined by the following calculation:
T_Edge_Time = C_Edge_Time + P_Delay_Data * Delay_Cell_Time。
where t_edge_time represents the last Edge occurrence Time compared to the occurrence Time after the initial Time T0, c_edge_time represents the coarse Delay Time, p_delay_data represents the fine Delay Data, and delay_cell_time represents the Delay value of a single element of the Delay chain.
Preferably: the 6 channel edge generators are respectively marked as a D0 channel edge generator, a D1 channel edge generator, a D2 channel edge generator, a D3 channel edge generator, a C0 channel edge generator and a C1 channel edge generator, and the D0 channel edge generator is used for switching the channel into an open state when the channel is in an off state. The D1 channel edge generator is used for switching the channel output state to a driving data corresponding state, the D2 channel edge generator is used for switching the channel output to a return state or a surrounding state, the D3 channel edge generator is used for switching the channel to a high-resistance state or closing the channel when the next period is a comparison period, the C0 channel edge generator is used for starting a comparison window or serving as a channel comparison gating signal, and the C1 channel edge generator is used for closing the comparison window.
Preferably: the test processor comprises a time sequence generator, a test pattern generator, a signal processing unit control instruction generator, a test pattern memory and a memory controller, wherein:
the test pattern memory is used for storing test pattern file information.
The time sequence generator is used for accessing the test graphic memory through the memory controller to acquire the time sequence requirement specified by the graphic file, and generating accurate time sequence signals required by each period according to the time sequence requirement specified by the graphic file.
The test pattern generator is used for accessing the test pattern memory through the memory controller to acquire the instruction requirement of the pattern file, and generating control time sequence required by pattern test according to the instruction requirement of the pattern file and the accurate time sequence signal required by each period.
The signal processing unit control instruction generator is used for accessing the test graphic memory through the memory controller to obtain graphic file control requirements, and generating instruction signals for synchronously controlling the digital channel test subsystem according to the graphic file control requirements and control time sequences required by graphic test.
Preferably: the delay chain output selector is connected with a first-stage calibration delay chain.
Compared with the prior art, the invention has the following beneficial effects:
1. the random time sequence waveform test signal can be generated at high speed under the control of the test processor, and the comparison and judgment of the test result can be completed in real time.
2. Test signals with high-precision edge information can be generated in real time, and the edge resolution can be within 50 ps.
3. The acquisition and analysis of the time information and the test information of the signals can be performed in real time. The time information acquisition resolution can be within 1 ns.
Drawings
FIG. 1 is a schematic diagram of the internal structure of a test processor.
FIG. 2 is a diagram of a test processor and a channel timing generator.
FIG. 3 is a schematic diagram of single channel digital timing waveform synthesis.
Fig. 4 is a schematic diagram of a channel output waveform implemented by each channel edge generator.
Fig. 5 is a schematic diagram of a channel edge generator.
Detailed Description
The present invention is further illustrated in the accompanying drawings and detailed description which are to be understood as being merely illustrative of the invention and not limiting of its scope, and various equivalent modifications to the invention will fall within the scope of the appended claims to the skilled person after reading the invention.
A high-precision program-controlled digital time sequence waveform generating device is shown in fig. 2, and comprises a test processor 1 and more than two channel time sequence generators 2, wherein the incoming line ends of the channel time sequence generators 2 are respectively connected with the test processor 1, and the outgoing line ends of the channel time sequence generators 2 are respectively connected with an electronic pin chip 3.
As shown in fig. 1, the Test Processor 1 (TP) is a typical von neumann architecture Processor, but the instruction set employs an ATE-specific instruction set, which is dedicated to processing signals, not data. A timing generator for controlling and synchronizing the various channels. The test processor 1 includes a timing generator 11, a test pattern generator 12, a signal processing unit control instruction generator 13, a test pattern memory 15, a memory controller 16, wherein:
a test Pattern memory 15 (Pattern memory) for storing test Pattern file information, which stores compiled test Pattern file codes.
The timing generator 11, the test pattern generator 12, and the signal processing unit Control instruction generator 13 access the test pattern Memory 15 through a Memory controller (Memory Control) 16 to acquire instructions and data.
A Timing Generator 11 (TG for short) for accessing the test pattern memory 15 through the memory controller 16 to obtain Timing requirements specified by the pattern file, generating accurate Timing signals (including periods, time edges, etc.) required for each period according to the Timing requirements specified by the pattern file, and providing the accurate Timing signals to other modules.
The test pattern generator 12 (Pattern Generator) is used for accessing the test pattern memory 15 through the memory controller 16 to obtain the instruction requirement of the pattern file, and generating control time sequences (including jump, loop and the like) required by the pattern test according to the instruction requirement of the pattern file and the accurate time sequence signal required by each period. Is responsible for executing instruction requirements in the Pattern file, implementing jumps, loops, etc., while controlling address access of the memory controller 16 to the test graphics memory 15.
The signal processing unit controls the command generator 13 (SPU CMD Generator) for accessing the test pattern memory 15 through the memory controller 16 to obtain the pattern file control requirements, and generating command signals for synchronously controlling the digital channel test subsystem according to the pattern file control requirements and the control timing required for the pattern test.
The signal processing unit control instruction generator 13 sends the control instruction of the test subsystem to the corresponding subsystem under the control of the test pattern generator 12, so as to realize the synchronous control of the subsystems.
As shown in fig. 2, the channel Timing generator 2 (PTG) includes an Edge generator 21 (Edge Gen, EG), a WaveForm generator 22 (wave form Gen, WFG), a Test Result generator 23 (Test Result Gen, TRG), a time recorder 24 (Time Measure Unit, TMU), and a History recorder (History Ram, HRam), wherein:
a test processor 1 for controlling and synchronizing the channel timing generator 2 of the respective channels.
An Edge generator 21 (Edge Gen, EG) for generating edges of the periodic and generated data waveforms.
A WaveForm generator 22 (WFG for short) for generating a specified data output WaveForm control signal by each edge combination according to the WaveForm format for the electronic pin chip 3 to generate an actual physical WaveForm.
A Test Result generator 23 (TRG) for generating a comparison Result with expected data based on the comparison signal returned from the electronic pin chip 3, to form a Fail signal for use by the Test processor.
The Time recorder 24 (THU) is used for recording the Time and data History information of the tested signal.
The Electronic Pin chip 3 (PE for short) is configured to generate an output signal according to the level specification ViH/ViL according to a control signal generated by the WFG, or convert a comparison result between VoH/VoL and the input signal into CmpH/CmpL for the test result generator 23 to process. I.e., for generating a drive test signal recognizable by the DUT from the drive control waveform signal or converting the output of the DUT into a test signal recognizable by the timing generator (cmp_h/cmp_l).
As shown in fig. 3, the channel timing generator 2 is a 6-channel timing generation module. The 6-channel timing generation module includes 6 channel edge generators 601 (Channel Edge Generator, abbreviated as CEG), a periodic edge generator 602, a driving waveform generator 604, a test result generator 605, a time measurement unit 606, and a history memory 607.
As shown in table 1, 6 channel edge generators 601 (Channel Edge Generator, abbreviated as CEG) are respectively designated as a D0 channel edge generator, a D1 channel edge generator, a D2 channel edge generator, a D3 channel edge generator, a C0 channel edge generator, and a C1 channel edge generator, and the D0 channel edge generator is used for switching the channel to an on state when the channel is in an off state. The D1 channel edge generator is used for switching the channel output state to a driving data corresponding state, the D2 channel edge generator is used for switching the channel output to a return state or a surrounding state, the D3 channel edge generator is used for switching the channel to a high-resistance state or closing the channel when the next period is a comparison period, the C0 channel edge generator is used for starting a comparison window or serving as a channel comparison gating signal, and the C1 channel edge generator is used for closing the comparison window.
Table 1 the meaning of each Edge is as follows:
Figure SMS_1
an illustration of the generation of drive control information by each channel edge generator is shown in fig. 4, and various waveform formats are illustrated in table 2.
Table 2 various waveform format illustrations
Figure SMS_2
A cycle edge generator 602 (Period Edge Generator, PEG for short) is configured to generate each cycle edge, and each cycle edge is called an initial time t0_edge of one cycle.
The driving waveform generator 604 (Drive Waveform Formatter, DWF for short) selectively outputs a driving control waveform signal for controlling the PE according to each edge and waveform format.
The test result generator 605 (Test Result Generator, abbreviated as TRG) is configured to generate a test result fail_Out according to the input CMP_H/CMP_ L, C0/C1 Edge of the PE and related signals, so as to provide the test processor and the subsequent modules with test result processing.
The time measurement unit 606 (Time Measure Unit, abbreviated as TMU) is configured to collect and measure the time information of the cmp_h/cmp_l in real time.
A History memory 607 (HRAM for short) is used to record the information (including the period, pattern address, test result, etc.) of each period test process in real time.
As shown in fig. 5, the channel Edge generator 601 (Channel Edge Generator, abbreviated CEG) includes a precise Edge data generator 6011 (Precise Edge Data Gen, abbreviated PEDG), a coarse Delay Edge generator 6012 (Crude Edge Gen, abbreviated CEG), a Delay chain output selector 6013 (Delay Line Mux, abbreviated DLM), and a Delay chain unit 6014 (Delay Line Cell, abbreviated DLC), wherein:
a precise edge data generator 6011 (Precise Edge Data Gen, abbreviated as PEDG) for precisely delaying the coarse delay edge to generate the required delay chain output selector 6013 inputs data.
A coarse delay Edge generator 6012 (CEG for short) for generating coarse delay edges that differ from the final edges by a fine delay time.
Delay chain output selector 6013 (DLM for short) is used for completing the accurate Delay of the coarse Delay, and the specific Delay time is specified by the accurate Delay data.
The last edge occurrence time compared to the occurrence time after T0 is determined by the following calculation:
T_Edge_Time = C_Edge_Time + P_Delay_Data * Delay_Cell_Time。
where t_edge_time represents the last Edge occurrence Time compared to the occurrence Time after the initial Time T0, c_edge_time represents the coarse Delay Time, p_delay_data represents the fine Delay Data, and delay_cell_time represents the Delay value of a single element of the Delay chain.
I.e. the final Edge occurrence time is multiplied by the delay value of the delay chain single unit by the coarse delay time plus the fine delay data.
A Delay chain unit 6014 (DLC for short) for generating a Delay value. Is the minimum delay unit of the delay chain. The delay value of each delay chain unit 6014 can be within 50ps according to the process condition.
In practical application, in order to solve the influence of temperature and other reasons on the delay chain, a first-stage calibration delay chain needs to be connected to the edge_q of the delay chain output selector 6013, and the functions of calibration or compensation and the like are realized through the first-stage calibration delay chain.
The foregoing is only a preferred embodiment of the invention, it being noted that: it will be apparent to those skilled in the art that various modifications and adaptations can be made without departing from the principles of the present invention, and such modifications and adaptations are intended to be comprehended within the scope of the invention.

Claims (8)

1. A high-precision program-controlled digital time sequence waveform generating device is characterized in that: the device comprises a test processor (1), more than two channel time sequence generators (2), wherein the incoming line ends of the channel time sequence generators (2) are respectively connected with the test processor (1), the outgoing line ends of the channel time sequence generators (2) are respectively connected with an electronic pin chip (3), and the channel time sequence generators (2) comprise an edge generator (21), a waveform generator (22), a test result generator (23) and a time recorder (24), wherein:
the test processor (1) is used for controlling and synchronizing a channel timing generator (2) of each channel;
the edge generator (21) is used for generating a period and generating an edge of a data waveform;
the waveform generator (22) is used for generating a designated data output waveform control signal through each edge combination according to a waveform format and generating an actual physical waveform by the electronic pin chip (3);
the test result generator (23) is used for generating a comparison result with expected data according to a comparison signal returned by the electronic pin chip (3) to form a Fail signal for the test processor;
the time recorder (24) is used for recording time and data history information of the tested signal;
the electronic pin chip (3) is used for generating an output signal conforming to the ViH/ViL level standard according to a control signal generated by the WFG, or converting a comparison result of VoH/VoL and the input signal into CmpH/CmpL for processing by the test result generator (23).
2. The high-precision programmable digital time sequence waveform generating device according to claim 1, wherein: the channel timing generator (2) is a 6-channel timing generation module.
3. The high-precision programmable digital time sequence waveform generating device according to claim 2, wherein: the 6-channel time sequence generation module comprises 6 channel edge generators (601), a periodic edge generator (602), a driving waveform generator (604), a test result generator (605), a time measurement unit (606) and a history storage (607);
the period edge generator (602) is used for generating each period edge, and each period edge is called an initial time T0_edge of one period;
the driving waveform generator (604) selectively outputs driving control waveform signals for controlling the electronic pin chip (3) according to the edges and the waveform format;
the test result generator (605) is used for generating a test result fail_out according to the input CMP_H/CMP_ L, C0/C1 Edge of the electronic pin chip (3) and related signals;
the time measurement unit (606) is used for collecting and measuring the time information of the CMP_H/CMP_L in real time;
a history memory (607) is used to record information for each cycle of the test procedure in real time.
4. A high precision programmed digital time sequence waveform generating apparatus according to claim 3, wherein: the channel edge generator (601) comprises a precise edge data generator (6011), a coarse delay edge generator (6012), a delay chain output selector (6013), and a delay chain unit (6014), wherein:
the accurate edge data generator (6011) is used for carrying out accurate delay on the coarse delay edge and outputting data input by the selector (6013) of a delay chain required by generation;
-said coarse delay edge generator (6012) is arranged to generate a coarse delay edge which differs from the final edge by a fine delay time;
the delay chain output selector (6013) is used for finishing the accurate delay of the coarse delay;
the delay chain unit (6014) is used for generating a delay value.
5. The high-precision programmable digital time sequence waveform generating device according to claim 4, wherein: the delay chain output selector (6013) is used for completing the accurate delay of the coarse delay, and the final edge occurrence time is compared with the occurrence time after T0, and is determined by the following calculation:
T_Edge_Time = C_Edge_Time + P_Delay_Data * Delay_Cell_Time；
where t_edge_time represents the last Edge occurrence Time compared to the occurrence Time after the initial Time T0, c_edge_time represents the coarse Delay Time, p_delay_data represents the fine Delay Data, and delay_cell_time represents the Delay value of a single element of the Delay chain.
6. The high-precision programmable digital time sequence waveform generating device according to claim 5, wherein: the 6 channel edge generators (601) are respectively marked as a D0 channel edge generator, a D1 channel edge generator, a D2 channel edge generator, a D3 channel edge generator, a C0 channel edge generator and a C1 channel edge generator, wherein the D0 channel edge generator is used for switching the channel into an open state when the channel is in an off state; the D1 channel edge generator is used for switching the channel output state to a driving data corresponding state, the D2 channel edge generator is used for switching the channel output to a return state or a surrounding state, the D3 channel edge generator is used for switching the channel to a high-resistance state or closing the channel when the next period is a comparison period, the C0 channel edge generator is used for starting a comparison window or serving as a channel comparison gating signal, and the C1 channel edge generator is used for closing the comparison window.
7. The high-precision programmable digital timing waveform generator of claim 6, wherein: the test processor (1) comprises a time sequence generator (11), a test pattern generator (12), a signal processing unit control instruction generator (13), a test pattern memory (15) and a memory controller (16), wherein:
the test pattern memory (15) is used for storing test pattern file information;
the time sequence generator (11) is used for accessing the test graphic memory (15) through the memory controller (16) to acquire the time sequence requirement specified by the graphic file and generating accurate time sequence signals required by each period according to the time sequence requirement specified by the graphic file;
the test pattern generator (12) is used for accessing the test pattern memory (15) through the memory controller (16) to obtain the instruction requirement of the pattern file, and generating control time sequences required by pattern test according to the instruction requirement of the pattern file and the accurate time sequence signal required by each period;
the signal processing unit control instruction generator (13) is used for accessing the test graphic memory (15) through the memory controller (16) to obtain graphic file control requirements, and generating instruction signals for synchronously controlling the digital channel test subsystem according to the graphic file control requirements and control time sequences required by graphic test.
8. The high-precision programmable digital timing waveform generator of claim 7, wherein: the delay chain output selector (6013) is connected with a first-stage calibration delay chain.
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