JPS6166283A - Address selection circuit - Google Patents

Abstract

PURPOSE:To reduce the ratio of area of an address bus to the entire part of an integration circuit by using a shift circuit and a comparator to constitute an address selection circuit and supplying serially the address information in order to supply an address through a single signal line. CONSTITUTION:An address selection circuit consists of shift circuits 60-68 and comparators 70 and 71-78, and the circuits 60-68 are preset at H by a preset signal 2. The serial address information 00000000, etc. is supplied from an address bus 1, and the circuits 60-68 start actions synchronously with an internal clock in response to a start bit 0. When the final bit of the address information is supplied and coincident with the address information to be selected and set by comparators 70 and 71-78. A selection signal of a high level is delivered from a NOR gate 8 for selection of the corresponding circuit. Thus the ratio of area of the bus 1 is reduced to the entire part of an integration circuit owing to such a constitution where the serial address information is supplied through a single signal line.

Description

[Detailed description of the invention] (Industrial application field) The present invention relates to address selection circuits within integrated circuits.

(Prior Art) Conventionally, address information was expressed in parallel signals inside an integrated circuit, which required an address bus composed of a plurality of signal lines. Therefore, there is a drawback that a large area for passing the address path occupies the limited area inside the integrated circuit.

(Objective of the Invention) An object of the present invention is to solve the above-mentioned drawbacks by expressing address information conventionally expressed in parallel signals in a serial signal, and to reduce the proportion of the address bus occupied inside an integrated circuit. 6. To provide a selection circuit.

(Structure of the Invention) The structure of the present invention is to time-divisionally input a plurality of address information (including a serial signal) into an address selection circuit built in an integrated circuit, and input the serial signal to a clock signal inside the integrated circuit. It has a shift circuit that stores specific address information to be selected, a memory circuit that stores specific address information to be selected, and a comparison circuit that compares the output of this memory circuit with the output of the shift circuit. Entering information is a feature.

(Principle and operation of the invention) In the present invention, by using a serial signal for address selection, the number of address buses is reduced to one, the area occupied by the address bus is reduced, and the area of the lk product circuit is reduced. This is what I did.

This 7real signal is composed of control information such as a start signal and address information, and is connected to the 77t circuit of each address selection circuit. At this time, since the address path connected to each address selection circuit is a serial signal, 1
The serial signal input to each shift circuit is sequentially converted by the clock signal inside the integrated circuit, and
It is further connected to a comparison circuit, in which it is compared with the address assigned to each address selection circuit,
If the address matches, a select signal is output to select the address.

(Example) Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

In this figure, there is an address bus 1 to which predetermined address information is given at a predetermined timing, and each address selection circuit 300, 30 that receives input from this address path 1.
1,302 to 3FF and these address selection circuits 300
, 301, 302 to 3FF output select signal 400,
401,402-4FF selected circuit 500.50
It consists of 1,502-5FF. Furthermore, the address selection circuits 300, 301, 302 to 3FF, as shown in the circuit diagram of FIG. 60 degrees 61 to 68, and comparators 70.71 to 78 connected to the outputs of these shift circuits 60, 61 to 68 and storing address information to be selected;
N0 whose input is the output of these comparators 70゜71 to 78
a8, and the output of this N0R8 becomes an output select signal.

Here, the case where address ro 1 (1@)J is selected will be explained using a time chart of tJ&3 Ca)*Cb> as an example. In this embodiment, the 8 bits following the start bit "O" are as shown in Figure 3 (a).

Since it represents address information, the address ro 1 (mJ
The information is expressed by a 7 real signal of roooooooolJ. The shift circuits 60, 61 to 68 are preset to 0 "1" by the I & first preset signal 2, and start operating when the start pitch (roJ) is input, synchronized with the clock signal inside the integrated circuit, and sequentially serial Shift the signal. Each address selection circuit 300゜301.302~
In the 3FF, the outputs of the shift circuits 60.61-68 are compared with pre-assigned address information to be selected by comparators 70.71-78. When the final bit of the serial signal r000000001J containing address information is input to each address selection, the select signal which is the output of the address selection circuit 301 matches the address information to be selected and the outputs of the 77 circuits 60, 61 to 68. 401 becomes rHJ level (FIG. 3(b)) and selects an address.

In this embodiment, addresses can now be selected using a single address bus instead of the one that required eight address buses.
The area occupied by the bus is reduced.

(Effects of the Invention) As explained above, the present invention expresses address information as a serial signal, uses t-1 address bus, and configures an address selection circuit with a shift circuit and a comparator.・Since the area occupied by the bus in the entire integrated circuit can be reduced, especially when the number of inputs is large,
Suitable for address selection circuits with a small number of outputs.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram of the address selection circuit 301 in FIG. 1, and FIGS. 3(a) and 3(b) are time charts of FIG. 1. Out. In the figure, 1... Address bus, 2... Preset signal, 300, 301, 302 to 3FF...
Address selection circuit, 400.401,402~4FF・
...Address selection circuit output (select signal) 1
．． :+00,501+502~51F...Circuit selected by address selection circuit, 60,61°62.6
3, 64, 65, 66. 67. 68 7 foot (ro) road, 70. 71, 72, 73, 74, 75, 7
6.77.78... Comparator, 8...9
Human power NOR. It is. 'PJ mouth

Claims (1)

[Claims] In an address selection circuit built into an integrated circuit, a shift circuit inputs a serial signal including a plurality of address information in a time-division manner and shifts this serial signal using a clock signal inside the integrated circuit, and a shift circuit that selects a specific address to be selected. An address selection circuit comprising a memory circuit for storing information and a comparison circuit for comparing an output of the memory circuit with an output of the shift circuit, and inputting address information from a single signal line.