JPS6165766U - - Google Patents

Info

Publication number
JPS6165766U
JPS6165766U JP1984149901U JP14990184U JPS6165766U JP S6165766 U JPS6165766 U JP S6165766U JP 1984149901 U JP1984149901 U JP 1984149901U JP 14990184 U JP14990184 U JP 14990184U JP S6165766 U JPS6165766 U JP S6165766U
Authority
JP
Japan
Prior art keywords
layer
electrode
junction
emits
interface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1984149901U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1984149901U priority Critical patent/JPS6165766U/ja
Publication of JPS6165766U publication Critical patent/JPS6165766U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49107—Connecting at different heights on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4918—Disposition being disposed on at least two different sides of the body, e.g. dual array

Description

【図面の簡単な説明】
第１図及び第２図は本考案の実施例を示す断面
図及び等価回路図であり、第３図は従来例を示す
回路図である。 １１……第１基板、１２……第１ｎ層、１３…
…第１ｐ層、１４……第２ｐ層、１５……第２ｎ
層、１６……第１の赤色発光接合（第１ｐｎ接合
）、１７……第１の緑色発光接合（第２のｐｎ接
合）、１８……第１電極、１９……第２電極、２
０……第３電極、２１……第２の基板、２２……
第３ｐ層、２３……第３ｎ層、２４……第４ｎ層
、２５……第４ｐ層、２６……第２の赤色発光接
合（第３のｐｎ接合）、２７……第２の緑色発光
接合（第４のｐｎ接合）、２８……第４電極、２
９……第５電極、３０……第６電極。

Claims (1)

    【実用新案登録請求の範囲】
  1. 第１の半導体基板上に第１ｎ層、第１ｐ層、第
    ２ｐ層、第２ｎ層を順次積層し上記第１ｎ層と第
    １ｐ層との界面は第１の発光色を発する第１のｐ
    ｎ接合となり、上記第２ｐ層と第２ｎ層との界面
    は第２の発光色を発する第２のｐｎ接合となると
    共に上記第１の基板裏面と第２ｎ層上とに夫々形
    成された第１、第２電極及び上記第１、第２ｐ層
    に共通の第３電極を有する第１のＬＥＤと、第２
    の半導体基板上に第３ｐ層、第３ｎ層、第４ｎ層
    、第４ｐ層を順次積層し上記第３ｐ層と第３ｎ層
    との界面は上記第１の発光色を発する第３のｐｎ
    接合となり、上記第４ｎ層と第４ｐ層との界面は
    上記第２の発光色を発する第４のｐｎ接合となる
    と共に上記第２の基板裏面と第４ｐ層上とに夫々
    形成された第４、第５電極及び上記第３、第４ｎ
    層に共通の第６電極を有する第２のＬＥＤとを有
    し、上記第３電極と第６電極、上記第１電極と第
    ５電極及び上記第２電極と第４電極とは夫々電気
    的に接続されていることを特徴とする半導体発光
    装置。
JP1984149901U 1984-10-03 1984-10-03 Pending JPS6165766U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1984149901U JPS6165766U (ja) 1984-10-03 1984-10-03

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1984149901U JPS6165766U (ja) 1984-10-03 1984-10-03

Publications (1)

Publication Number Publication Date
JPS6165766U true JPS6165766U (ja) 1986-05-06

Family

ID=30708067

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1984149901U Pending JPS6165766U (ja) 1984-10-03 1984-10-03

Country Status (1)

Country Link
JP (1) JPS6165766U (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101645443A (zh) * 2008-08-05 2010-02-10 三星电子株式会社 半导体器件、含该半导体器件的半导体封装及其制造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101645443A (zh) * 2008-08-05 2010-02-10 三星电子株式会社 半导体器件、含该半导体器件的半导体封装及其制造方法

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