JPS6165647A - Circuit control circuit of packet exchange - Google Patents

Abstract

PURPOSE:To decrease a load off CPU, to improve processing capacity and to make data transmission highly speedily by dividing the data block received by URT to a prescribed length and installing plural DMA control means to transmit DMA, a DMA switching controller and a detecting means to detect ETX and ETB and a means to stop a DMA transfer. CONSTITUTION:First, by checking BCC by URT32, the presence and absence of the error of the transmitting data 31 are investigated. When an error is present the data are re-transmitted from a terminal 30. When the error is absent, a long data block is shortly divided by DMA controllers 33 and 34. Further, by switching the controllers 33 and 34 alternately, the short data block is successively DMA-transferred to the next step exchanger. When BCC is included in a data block, DMA transfer is executed from a detecting circuit 41 and a delay circuit 42 and the transfer of the data after that is prohibited.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides URT (υn1versaI Receiving
BSC (Blnary 5sync) using a line control LSI called erTrlnsmjtt15r
The present invention relates to a line control circuit for a packet switch that performs DMA transfer of data according to a chronous communications procedure.

[Conventional technology]

In general, a packet switch transfers data to
This is done link-by-link between each exchange, providing a high-quality transmission path. However, in order to correct errors, it is necessary to store data in blocks, and therefore it is recommended to transmit data in long data blocks. Therefore, the delay time characteristics are significantly worse compared to circuit switching. This will be explained in the case where data is transmitted from the terminal 1 to the host CPU 5 via the packet exchange 492.394, as shown in FIG. 3(a), for example. In this case, if the time it takes for the Kerat exchange 2.3.4 to relay data is t, it will take 4t for the data to reach the host CPU 5 from the terminal 1 (as shown in the figure). (However, in ζ and ζ, it is assumed that data is transmitted at the same speed at all locations, rounding is done to make the explanation easier).

In particular, when transmitting one stroke of data through conversational communication between a terminal and a host's CPU, it is generally said that the data is sent in long data blocks in order to increase transmission efficiency. But on the other hand, the response time is shortened)! ! It is also often desired to maintain good delay time characteristics.

To reduce response time, it is necessary to use URT in the packet switch.
By using error correction between terminals, i.e., end to end (End t.

Efid), line 5 circuit-switched service is requested,
It became necessary to divide long data blocks into shorter pieces and transmit them at high speed.

[Problem that the invention seeks to solve]

When trying to meet the above requirements with a conventional packet switch, the following problems arose. Figure 4 shows the time between
A specific example will be explained based on FIG.

With reference to FIG. 4, data block transmission using the URT will be explained, particularly the functions of the general URT. Here, the Kerat exchange 21 includes a reception side JURT 23 and a transmission side UFLT 24, and data from the terminal 20 is transmitted to the host CPU 22 via the packet exchange 21.The data from the terminal 20 is shown in FIG. It is sent in the general data transmission message format according to the BSC procedure as shown below. Here, STX is a code indicating the start of data, gTX or ETB is a code indicating the end of data, and BCC is a code indicating the end of data. STX to BTX
Or it is a code for error checking up to ETB.

Invalid data follows the BCC.

In FIG. 4, the above data from the terminal 20 is
10RT23 checks whether the BCC is correct or not, but this BCC is not transferred by DMA.

If the above data is correct, BTX up to ETB will be sent from the sending side URT24, and BCC will be sent from the sending side υRT.
It is added by 24. When the KBCC is added on the sending side, the same content as the received BCC is added to the transmitted data without DMA transfer of the BCC.

However, if K is the same length as the received long data block, as described above, K is the same length as the received long data block.
transfer time. On the other hand, in order to shorten the transfer time with
5 into short data blocks 26.27, it will be inconvenient if the BCC is not included as part of the data, but the above URT has the function of DMA transfer up to the BCC [ Therefore, data blocks cannot be divided into short sections and transferred as shown in FIG.

The URT also has a BTX or ETB detection function during DMA transfer, and upon detecting these, sends an interrupt instruction to the CPU. When the CPU receives this instruction, it uses the program transfer mode (2) to take over the BCC of the host and transfer the data to the D.
After MA transfer, BCC must be written in the area next to the area where gTB or BTX is stored. Therefore, the CPU must have multiple functions such as address classification.

Furthermore, it is required to perform the following five types of processing in real time according to the line speed. However, especially when accommodating multiple lines or high-speed lines, the load on the CPU increases, resulting in a significant drop in processing capacity, so it has been extremely difficult to achieve the above requirements.

[Means for solving problems]

The line control circuit according to the present invention uses URT-CBS.
DMA transfer of data according to the C procedure (applied to the Kerat exchange, and as a means to solve the above problem [, the data block received by the URT is divided into desired lengths) A plurality of DMA control means for DMA transfer, and a D of each divided data block.
Every time an MA transfer is completed, the DMA that performed the DMA transfer
a switching means for switching from the control means to any other DMA control means and connecting it to the υRT; a detection means for detecting BTX or ETB inserted before the BSC operation 0BCC to indicate the end of data; D
By providing means for stopping the A transfer, the BC
This allows DMA transfer up to C.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a line control circuit of a packet switch according to the present invention. At this point ζ, the URT 32 is connected to the terminal 30 and receives the transmission data 31 from the terminal 3o. This transmission data 31 is sent in the message format of general data transmission according to the circular SC procedure shown in FIG.

The URT 32 is connected to the CPU 40 IC via one of two DMA controllers 233, 34. By the way, the DMA controller 33 or 34
A predetermined number of bytes is set according to the instructions of U4G, and the URT
Divide the data received at 32 into short data consisting of this number of bytes, and send this one section of short data to data line 5.
DMA transfer from 0 or 51 to the next exchange. D
The M person controller 33 or 34 outputs a transfer end signal 38 or 39 when this DMA transfer is completed, and is connected so that this signal 38 or 39 is guided to the CPU 40 and the DM person switching controller 235.

The DM person switching controller 35 has a switching switch 36.3.
From switching 7, URT32 and cpu+o<
On the other hand, the two DMA controllers 33 and 34 are
This switching is performed at 9 o'clock when the transfer end signal 38 or 39 is received. Also, CPU
Upon receiving the transfer end signal 38 or 39, 40 simultaneously with the above switching, provides a predetermined number of bytes to the switched DMA controller 33 or 34.
Similarly, DMA transfer is performed using t pieces of short data as described above.

Further, the terminal 30 is connected to the CPU 40 via a detection circuit 41 and a delay circuit 42. Here detection port i%41
5 detects BTX or ETB indicating the end of data shown in FIG. 5, and sends the detection signal 43 to the delay circuit 42. The delay circuit 42 has a detection number 41 and a detection number 43.
In response, it waits for a predetermined period of time until the DMA transfer of the 2-byte BCC is completed, and then sends a BCC transfer end signal 43 to the CPU 40. CPU4Q uses this BC
Upon receiving the C transfer end signal 43, the DMA transfer is stopped. In this way, by delaying the BTX or ETB by the predetermined time after detection, after the BCC is transferred as data, the transfer of the next (invalid) data of the BCC is prohibited.

In this embodiment, first, when the URT 32 checks the BCC, the transmission data 31 is checked for errors.

If there is a step 2-, the data is retransmitted from the terminal 30. If there is no step 2-, do D as described above.
MA controllers 33 and 34 divide long data blocks into shorter blocks.

Then, by alternately switching the KDM controllers 33 and 34, short data blocks are sequentially DMA-transferred to the next-stage exchange. When a data block includes a BCC, the detection circuit 41 and the delay circuit 42 perform the DMA transfer up to the BCC, and subsequent data transfer is prohibited.

Next, as shown in No. Z@(a), a case will be described in which data from the host CPU 5Vc is transmitted from the terminal 1 via the packet switch 2, 3.4 having the line control circuit according to the present example. Here, long data from terminal 1 is 4
It is assumed that the data is divided into equal parts and DMA transfer is performed. In this case, the conventional method requires only a short time as shown in FIG.

In this case, the conventional processing capacity for one 9600bps line can be increased to 14 9600bps lines. In addition,
By dividing the data into smaller pieces, even higher processing power can be achieved.

In this example, two DM controllers 2 are provided, but by providing three or more, it is easier to set the number of bytes for dividing data into shorter pieces as described above, and data transfer is performed at even higher speeds. be able to.

〔Effect of the invention〕

As explained above, the present invention makes it possible to perform DMA transfer up to the BCC, thereby reducing the load on the C10 and improving the processing capacity, making it easy to perform real-time processing according to the line speed. Therefore, it has five important effects in enabling high-speed data transmission.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the circuit system #enro of a packet switch according to the present invention, FIG. 2 is an explanatory diagram of data transmission using the packet switch according to the present invention, and FIG. 3 is a diagram showing a conventional packet switch. An explanatory diagram of data transmission using a switch. Figure 4 is a block diagram of a nine-packet switch using a general URT. Figure 5 is a diagram showing a general data message format using the BSC procedure. Figure 6 is a diagram showing the format of a general data message using the BSC procedure. FIG. 3 is a diagram showing a state in which a block is divided into two short data blocks. 32...URT 33, 34...DMA control 4-235...-DMA switching fund draw')
36.37...Selector switch 40・-cpυ
41...Detection circuit 42...Slow circuit. Patent applicant: Nippon'#iKi Co., Ltd. -0,. Agent Patent Attorney Uchihara Akihito 6, -
1, No' Figure 2 Figure 3 Figure 4

Claims (1)

[Scope of Claims] In a line control circuit of a packet switch that performs DMA transfer of data according to a BSC procedure using a URT, a plurality of DMAs divide a data block received by the URT into predetermined lengths and transfer the divided data by DMA. a control means; a switching means for switching from the DMA control means that performed the DMA transfer to any other DMA control means and connecting to the URT each time the DMA transfer of each divided data block is completed; Detection means for detecting BTX or ETB inserted before the BCC in the BSC procedure to indicate the end of data, and issuing an instruction after a predetermined time from when the detection is made until the DMA transfer to the BCC is completed. By DM
1. A line control circuit for a packet switch, comprising means for stopping A-transfer.