CN115967589A

CN115967589A - ARM and FPGA-based high-speed buffer type CAN bus communication system and method

Info

Publication number: CN115967589A
Application number: CN202211469150.8A
Authority: CN
Inventors: 田英峰; 杨明洁
Original assignee: Xi'an Changyuan Electron Engineering Co ltd
Current assignee: Xi'an Changyuan Electron Engineering Co ltd
Priority date: 2022-11-22
Filing date: 2022-11-22
Publication date: 2023-04-14

Abstract

The invention relates to a high-speed buffer type CAN bus communication system and a method based on ARM and FPGA, wherein all components are designed by adopting home-made chips, a dual-port RAM is established in the FPGA to be connected with two ARM processors, and 2 annular buffer queues Queue-Tx1, queue-Tx2, queue-Rx1 and Queue-Rx2 are established in the two ARM chips; the Queue-Tx1 and the Queue-Rx1 are used as data exchange buffers with the FPGA chip, and the Queue-Tx2 and the Queue-Rx2 are used as buffers for CAN bus transceiving data; because the method of double buffer queues is adopted to process the transmission of the CAN bus with large data volume, the data receiving capacity and the data receiving and transmitting capacity of the CAN bus of the computer are greatly improved, and the data transmitting capacity reaches 11000 frames/second; the data receiving capacity reaches 14000 frames per second, the data sending and receiving can be obviously improved, 10000 frames are sent once without losing data, and the requirement of 100 frames cached by a user is met.

Description

ARM and FPGA-based high-speed buffer type CAN bus communication system and method

Technical Field

The invention belongs to the field of CAN bus communication, relates to a high-speed buffer type CAN bus communication system and method based on ARM and FPGA, and aims to solve the problems that in the process of transmitting large data volume, the CAN bus has overlong transmission time and low efficiency, and even loses data, so that a double-buffer CAN bus communication method is provided in a targeted manner.

Background

The CAN bus technology has the characteristics of automatic message filtering retransmission, extremely low bit error rate, high communication rate and the like, and is widely applied to the industrial and military fields. The current CAN bus interface card based on the PCIe interface has the problems of low data throughput rate, overlong transmission time and even data loss under the condition of needing to transmit a large amount of data in a burst mode. In a certain type of scout car, various equipment are connected through a CAN bus, and the load rate of CAN bus communication and the frame data sending amount are large, so that the high-speed large-data-amount CAN bus communication design needs to be realized.

In order to ensure the smooth research and development and production of equipment and ensure the information safety and the autonomous controllability of the equipment, the localization of the equipment is imperative. And because factors such as high and new technology sanctions, foreign chip productivity atrophy and the like influence, the design by using foreign chips is not suitable at present, and the existing equipment or newly-developed equipment needs to be subjected to domestic transformation or redesign, so that the aim of not being clamped by a neck is fulfilled.

Disclosure of Invention

Technical problem to be solved

In order to avoid the defects of the prior art, the invention provides a high-speed buffer type CAN bus communication system and method based on ARM and FPGA, all components are designed by adopting home-made chips, and are optimized and promoted by combining with a common scheme, so that the problems of equipment localization and data transmission stability and reliability under the condition of burst transmission of a large amount of data are solved. The hardware is designed into a PCIe communication board card provided with a dual-channel CAN bus. The board card is installed in a domestic case and is communicated with a computer through a PCIe interface for data interaction.

Technical scheme

The utility model provides a high-speed buffer type CAN bus communication system based on ARM and FPGA which characterized in that: the system comprises a PCIe bus-to-parallel local bus chip, a programmable gate array chip FPGA and two ARM processors based on a Cortex-M3 architecture; a dual-port RAM is established in the FPGA and connected with two ARM processors, one port is connected with a PSMC bus port of ARM-1 and transmits address bus and MEM data, and the other port is connected with a PSMC bus port of ARM-2 and transmits the address bus and the MEM data; the connection ports between the FPGA and the PCIe bridge chip are address buses, MEM data and I/O data lines, and the connection ports with the two ARM processors are also provided with I/O data lines; the two ARM processors are respectively connected with the two CAN transceiver modules; four DPRAMs are established in the FPGA, wherein DPRAM-1 is allocated to upper computer writing, DPRAM-2 is allocated to upper computer reading, DPRAM-3 is allocated to lower computer writing, and DPRAM-4 is allocated to lower computer reading.

A communication method adopting the high-speed buffer type CAN bus communication system based on ARM and FPGA is characterized in that: 2 annular buffer queues Queue-Tx1, queue-Tx2, queue-Rx1 and Queue-Rx2 are established in the two ARM chips; the Queue-Tx1 and the Queue-Rx1 are used as data exchange buffers with the FPGA chip, and the Queue-Tx2 and the Queue-Rx2 are used as buffers for CAN bus transceiving data; the communication steps are as follows:

when the upper computer sends data, the data are sequentially sent to a primary buffer Queue-Tx1 and a secondary buffer Queue-Tx2 of the ARM chip from the FPGA dual-port RAM, and the CAN controller takes out the data from the secondary buffer Queue-Tx2 according to frames and sends the data to the CAN bus;

when the CAN bus receives data, judging the validity of the data, inputting the data into the FPGA dual-port RAM through a secondary buffer Queue-Rx2 and a primary buffer Queue-Tx1 of the ARM in sequence, and reading the data from the dual-port RAM to a CPU memory unit for processing through a DMA mode by the upper computer.

The process of sending data by the upper computer is as follows: 1) The upper computer writes data to be sent into a DPRAM-1 in a DMA mode, and the FPGA informs an ARM to read the data in an external interrupt mode; 2) After the ARM receives an interrupt signal, data are temporarily stored in a primary buffer Queue-Tx1 through an FSMC bus, when in a main processing process, the ARM checks whether unread data exist in the primary buffer Queue-Tx1 in each cycle, if yes, the data are transferred from the primary buffer Queue-Tx1 to a secondary buffer Queue-Tx2, the data are taken out from the secondary buffer Queue-Tx2 in idle time according to frames, and a CAN bus controller is called to sequentially send the data to a CAN bus.

The process of receiving data by the upper computer is as follows: 1) When data arrive in the CAN bus, storing the data into a secondary buffer Queue-Rx2 through CAN interruption, setting a 5ms timer in a program, when the 5ms timer arrives, transferring the buffer data in the secondary buffer Queue-Rx2 into a primary buffer Queue-Rx1, and generating an interruption signal through I/O (input/output) to send an FPGA (field programmable gate array); 2) After receiving the interrupt signal, the FPGA transfers the data in the Queue-Rx1 to the DPRAM-2 through the FSMC bus, and generates PCIe interrupt to inform an upper computer to read.

Advantageous effects

The invention provides a high-speed buffer type CAN bus communication system and method based on ARM and FPGA, which is a high-speed CAN bus communication method realized by using two-stage buffer queues.

Through experimental verification, the same hardware ARM chip is used, no buffering processing is performed in software, and a data buffering mode is performed through a hardware internal buffering unit, so that when a computer sends 100 frames of data once, the CAN bus equipment CAN only receive 17 frames of data, and the rest 83 frames of data are lost.

Because the invention adopts a double-buffer queue method to process the transmission of the CAN bus with large data volume, the data receiving capacity and the data receiving and transmitting capacity of the CAN bus of the computer are greatly improved, and the data transmitting capacity reaches 11000 frames/second; the data receiving capacity reaches 14000 frames per second, the data sending and receiving can be obviously improved, 10000 frames are sent once without losing data, and the requirement of 100 frames cached by a user is met. A comparison of this board card and similar equipment is shown in table 1.

TABLE 1 comparison of the present invention with similar equipment parameters

Drawings

FIG. 1: principle block diagram of the invention

Detailed Description

The invention will now be further described with reference to the following examples, and the accompanying drawings:

the core idea of the invention is as follows:

the main processing chips adopted by the invention are CH368 (PCIe bus-parallel local bus), FMK50T4 (FPGA field programmable gate array chip), GD32F103VET6 (based on Cortex-M3 architecture ARM processor chip) and peripheral interface chip, etc.

Establishing a dual-port RAM in the FPGA, establishing a two-stage annular buffer queue in the ARM, when the upper computer sends data, sequentially storing the data in the dual-port RAM, the ARM first-stage buffer and the ARM second-stage buffer, and finally taking out the data from the second-stage buffer according to frames and sending the data to a CAN bus by the CAN controller; when the CAN bus receives data, the data is stored in the ARM secondary buffer, the ARM primary buffer and the dual-port RAM in sequence after the legality of the data is judged, and the upper computer reads the data from the dual-port RAM to the CPU memory unit for processing in a DMA mode.

The communication block diagram of the CAN bus is shown in the attached drawing.

The method comprises the following steps:

the communication method of the dual channel is the same, so the following description is made in terms of the method of single channel communication.

[1] 2 independent dual-port RAM block storage spaces are established in the FPGA, and the dual-port RAM (DPRAM) spaces are set to have read-write bandwidths of 32 bits and a depth of 8KB. Wherein 1 RAM block is allocated to the upper computer for writing and is defined as DPRAM-1; the other 1 RAM block is allocated to the upper computer for reading and is defined as DPRAM-2.

[2] 4 circular buffer queues Queue-Tx1, queue-Tx2 and Queue-Rx1 and Queue-Rx2 are established in the ARM chip. The Queue-Tx1 and the Queue-Tx2 are data buffers sent by an upper computer; the Queue-Rx1 and the Queue-Rx2 are used for buffering the data received by the upper computer. The Queue-Tx1 and Queue-Rx1 are used as data exchange buffers with the FPGA chip, and the Queue-Tx2 and Queue-Rx2 are used as buffers for CAN bus transceiving data.

[3] The process of sending data by the upper computer: the upper computer software writes data to be sent into a DPRAM-1 in a DMA mode, an FPGA informs an ARM to read the data in an external interrupt mode, the ARM temporarily stores the data into a Queue-Tx1 through an FSMC bus after receiving the interrupt, the ARM checks whether unread data exist in the Queue-Tx1 in each cycle in a main processing process, if yes, the data are transferred into a Queue-Tx2 from the Queue-Tx1, the data are taken out from the Queue-Tx2 in frames in idle time, and a CAN bus controller is called to sequentially send the data to a CAN bus.

[4] The process of receiving data by the upper computer: the CAN bus has data, the data are stored in the Queue-Rx2 through CAN interruption, a 5ms timer is set in a program, when the 5ms timer arrives, buffer data in the Queue-Rx2 are transferred to the Queue-Rx1, an interruption signal is generated through I/O, after the FPGA receives the interruption signal, the data in the Queue-Rx1 are transferred to the DPRAM-2 through the FSMC bus, and PCIe interruption is generated to inform an upper computer to read the data.

Claims

1. The utility model provides a high-speed buffer type CAN bus communication system based on ARM and FPGA which characterized in that: the system comprises a PCIe bus-to-parallel local bus chip, a programmable gate array chip FPGA and two ARM processors based on a Cortex-M3 architecture; a dual-port RAM is established in the FPGA and connected with two ARM processors, one port is connected with a PSMC bus port of ARM-1 and transmits an address bus and MEM data, and the other port is connected with a PSMC bus port of ARM-2 and transmits the address bus and the MEM data; the connection ports between the FPGA and the PCIe bridge chip are address buses, MEM data and I/O data lines, and the connection ports with the two ARM processors are also provided with I/O data lines; the two ARM processors are respectively connected with the two CAN transceiver modules; four DPRAMs are established in the FPGA, wherein DPRAM-1 is allocated to an upper computer for writing, DPRAM-2 is allocated to an upper computer for reading, DPRAM-3 is allocated to a lower computer for writing, and DPRAM-4 is allocated to a lower computer for reading.

2. A communication method using the ARM and FPGA based cache-type CAN bus communication system of claim 1, wherein: 2 circular buffer queues Queue-Tx1, queue-Tx2, queue-Rx1 and Queue-Rx2 are established in two ARM chips; the Queue-Tx1 and the Queue-Rx1 are used as data exchange buffers with the FPGA chip, and the Queue-Tx2 and the Queue-Rx2 are used as buffers for CAN bus transceiving data; the communication steps are as follows:

3. The method of claim 2, wherein: the process of the upper computer sending data is as follows: 1) The upper computer writes data to be sent into a DPRAM-1 in a DMA mode, and the FPGA informs an ARM to read the data in an external interrupt mode; 2) After the ARM receives an interrupt signal, data are temporarily stored to a primary buffer Queue-Tx1 through an FSMC bus, the ARM checks whether unread data exist in the primary buffer Queue-Tx1 in each cycle during a main processing process, if yes, the data are transferred from the primary buffer Queue-Tx1 to a secondary buffer Queue-Tx2, the data are taken out from the secondary buffer Queue-Tx2 in idle time according to frames, and a CAN bus controller is called to sequentially send the data to a CAN bus.

4. The method of claim 2, wherein: the process of receiving data by the upper computer is as follows: 1) When data arrive in the CAN bus, storing the data into a secondary buffer Queue-Rx2 through CAN interruption, setting a 5ms timer in a program, when the 5ms timer arrives, transferring the buffer data in the secondary buffer Queue-Rx2 into a primary buffer Queue-Rx1, and generating an interruption signal through I/O (input/output) to send an FPGA (field programmable gate array); 2) After receiving the interrupt signal, the FPGA transfers the data in the Queue-Rx1 to the DPRAM-2 through the FSMC bus, and generates PCIe interrupt to inform an upper computer to read.