JPS6165347A - Information processor - Google Patents

Abstract

PURPOSE:To reduce the load on a CPU due to the intervention of software interrupt processing and the load on a timer used for monitoring by bringing timer functions for monitoring serial transmission and reception under the control of one timer together. CONSTITUTION:The timer O16 which is started in response to automatic data transfer processing by a transmission I/O request outputs a timer-0 counting end signal 69 to a request control part 31 for I/O at specific intervals of time based upon a value set in a timer 0-modulo register 18. The I/O request control part 31 reports timer-0 automatic data transfer processing to an I/O request accepting part 32 and decreases the contents of a timer counter part (WDC)47 for monitoring an I/O request generating origin by one. When normal serial transmission is performed, reception completion is reported to a serial data transfer device 1 within a specific time to stop the subtraction of WDC47. On the other hand, if abnormality occurs in the serial transmission, the subtraction of EDC47 is not stopped and the value becomes 0, detecting 0.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a serial transmitting/receiving device capable of generating a transmission processing request or an information processing device having an internal serial interface circuit.

(Prior Art) Conventionally, in serial data transfer processing that respects time management, the serial interface generates an interrupt every time one data is transmitted/received, and the serial data transfer processing is performed by software processing of the CPU. The timer assigned to the serial interface monitors the time for normal serial transmission and reception processing, and in serial reception, it detects whether there is a reception take within a certain period of time when the other party's reception is completed within a certain period of time. 0 Next, an overview of serial data transfer processing using time monitoring using a conventional timer will be explained with reference to the block diagram of FIG. In the figure, 1 is a serial data transfer device, 2 is an interrupt control section, 3 is an execution section, 4 is a program memory, 5 is a data memory, 6 is a timer, and 7 is an internal bus.

The serial data transfer device [1 has a sending buffer register 1 connected to a sending 2 in 61 and a receiving buffer register 2 connected to a receiving 2 in 62, and the sending/receiving control signal is a notification from the other party that reception is complete. A clear-to-send line 63 (hereinafter abbreviated as CTS) is provided to send data to the interrupt controller 2, and a data set-to-send line 64 (hereinafter abbreviated as DSR) to notify the other party of completion of reception. A signal 65 (hereinafter abbreviated as TxBE), a receive buffer register full signal 66 (hereinafter abbreviated as Rx HF), and a CT8 notification signal 67 are output.

Timer 6 monitors the time for normal serial transmission/reception processing
(hereinafter referred to as monitoring timer) consists of two timer unit timers (0), 16. Timer (consisting of 1117, timer O modulo register 18 for setting the count value, timer 1 modulo register 20, timer O timer register 19 for actually counting down, timer 1 timer register 21 and counter 22, interrupt control section 2, a timer count completion signal 68 and a timer 1 count completion signal 69 are output.

The interrupt request control unit 2 accepts the interrupt with the highest priority among them, since there are actually few interrupt requests from other peripheral hardware. (hereinafter abbreviated as PC), a 10G2 system status word 14 (hereinafter abbreviated as PSW), and a general-purpose register cell 15.

A conventional microcomputer with a built-in serial interface is composed of a program memory 4 for storing interrupt processing programs, etc., and a data memory 5 for holding transmission/reception processing data, which are interconnected by an internal path 7. ing.

The data memory 5 also includes a transmission data storage area C that is required for software processing based on transmission/reception interrupts in advance;
A transmission parameter save area A1 reception data storage area that stores address information that specifies this transmission data storage area and transmission count information, and a reception parameter save area that stores address information that specifies this reception data storage area and reception count information. B is set.

First, a serial transmission interrupt processing procedure having a time monitoring function using a timer will be explained.

Here, a timer (0116) is assigned as a monitoring timer, and a predetermined monitoring time (time from completion of transmission to notification of reception completion by the other party) is set in advance in the timer O module LLj register 18.
Set the count value to obtain. The transmission data in the transmission buffer register 11 is output to the outside through the transmission 2 input 61, and when the transmission buffer register 11 becomes empty, the serial data transfer device 1 outputs the TxBE65tl-
It is activated to notify the interrupt control unit 2 that the transmission buffer completion register is empty.

Next, the interrupt control section 2 activates the interrupt request line 68 to notify the execution section 3 of the occurrence of a transmission interrupt request, and the execution section 3 accordingly executes transmission interrupt processing.

This interrupt boobis first saves the contents of the program processing up to that point to the PCIB, P8W14, and general-purpose register set 150 internal address stack, and reads the address of the transmit data storage area C from the transmit parameter save area A. and load it into the pointer. Next, the transmission data is read from the transmission data storage area C specified by the pointer and stored in the transmission buffer register 11, and
A start signal is sent to timer q(0)16 assigned as a monitoring timer. In response to the start signal, this timer +0116 reloads the count value of the timer 0 modulo register 18, which is set at a predetermined time interval, into the timer 0 timer register 19, and starts decrementing the timer modulo register 16. The transmission interrupt service next checks the number of transmissions, and if the number of transmissions does not reach a predetermined number, updates the address information and number of transmissions in the transmission data storage area C, returns them to the transmission parameter save area A, and then updates the general-purpose register set 15. , P8W14 ,
PC13t-returns and completes the transmission interrupt service.

Furthermore, when the number of transmissions reaches a predetermined number, the process branches to transmission procedure completion processing.

If normal serial transmission is performed, timer +0116, which is a timer for monitoring
Before outputting the timer zero count completion signal 69 to the interrupt control unit 2, the other party completes normal reception and activates the CT863. The serial data transfer device 1 outputs a CT8 notification signal 67 to the interrupt control section 2, and the execution section 3 performs pcT8 interrupt processing. This interrupt service is PCl3, P8W14. After saving the general-purpose register set 15, he straggles the timer (006) and returns to the general-purpose register set 15.PSW14.PC13f: to complete the interrupt service.

Additionally, if the CT863 does not become active within a predetermined time interval, an interrupt is activated by the timer count completion signal 69 of the timer (006), and the CPU detects that an abnormality has occurred in the serial transmission process. be able to.

Next, in serial reception, the monitoring timer is assigned a timer (1117), and the timer 1 modulo register 2 is assigned.
A predetermined monitoring time (data reception time interval) is set in advance to 0 and started at the same time as the serial reception operation starts.

The timer (1) 17i reads the count value of the timer 1 modifier register 2o, in which a predetermined monitoring time interval is set in advance, into the timer 1 timer register 21 in response to the I start signal. Start decrementing the register 21.

If normal serial reception is performed, the timer (IJ17
interrupts the timer 1 count completion signal 70f to the control unit 2.
: Reception of received data (storage to N-back completion register 12 is completed before outputting. Serial data transfer device 1 outputs RxBF35 to interrupt intelligence control unit 2, and execution unit 3
collects reception interrupt processing.

This interrupt service saves the contents of the PCI 3, P8'W14° general-purpose register set 15 to the stack, and then stops the timer (1117).Next, the address from the receive parameter save area B to the receive data storage area is is loaded into the pointer, the received data is read from the 9-bit buffer register 12, and stored in the received data storage area specified by the pointer.Then, D8R64t is activated to notify the recipient of the completion of reception, and the timer +11 is activated.
Send a start signal to 17. The timer (1117) receives the start signal, initializes the count value, and then restarts the countdown.

The reception interrupt service then checks the number of receptions, and if the predetermined number of receptions has not been completed, updates the address information and reception image A candy in the reception data storage area and returns them to the reception parameter save area B. . He then restores the general-purpose register set 15, PAW14, and PCl3 to complete the interrupt service. When the number of receptions reaches a predetermined number, the process branches to reception procedure completion processing.

In addition, if normal serial data reception is not performed within a predetermined time interval and no reception completion interrupt occurs, the timer 1 output of timer 11+17 completes the count completion signal 70.
The bcpu can detect an abnormality in serial reception processing by the occurrence of an interrupt.

As explained above, serial transmission/reception processing with a timer monitoring function in conventional microcomputers involves 1) realizing serial data transfer processing and control of the monitoring timer by software processing using interrupts, and 2) implementing the monitoring function. This method has drawbacks such as requiring as many timers as the number of serial transmitting/receiving hardware required.

In interrupt processing, the overhead associated with saving and recalling the program counter, program status word, and general-purpose register set accounts for 9 percent of all 1!11 inclusive service routines, and this is
This reduces U's main processing time and reduces processing capacity. In addition, since two timers are already used in serial transmission and reception), the unique functions of the timers are firmly used. Furthermore, if there is peripheral hardware that requires a monitoring function using other timers, multiple timers are required, which leads to an increase in chip width and a decrease in yield.

(Objective of the Invention) An object of the present invention is to solve these problems and improve serial data transfer in serial transmission/reception equipped with a monitoring function.
In addition to realizing the control of the monitoring timer by hardware, it is often possible to control the monitoring/fma function of each serial transmission/reception all at once with one timer, and to interrupt the CPU by intervening with software interrupt processing. The object of the present invention is to provide an information processing device having a serial transmission/reception function with monitoring that reduces the burden on timers used for monitoring.

(Structure of the Invention) The 1vA configuration of the present invention includes a serial data transfer device that generates a transmission processing request associated with send processing and a reception processing request associated with reception processing, and a serial data transfer device that generates a gilt completion processing request upon completion of the timer side. In an information processing apparatus that includes a timer that generates a timer, a memory unit that stores transmitted/received data and a program, and a CPU that executes processing based on a transmission processing request, a reception processing approval, and a measurement completion processing request, The apparatus includes a data transfer processing means for performing data transfer processing corresponding to a transmission processing request and a reception processing request while maintaining the state of the CPU involved, and a serial transmission/reception abnormality occurrence detection means based on a measurement completion processing request of the timer. , when the serial data transfer device generates a transmission processing request and a reception processing request, the CPU performs predetermined transmission and reception data processing by the data transfer processing means and monitors transmission and reception data processing by the serial transmission and reception abnormality detection means. Features.

(Function of the Invention) In the present invention, serial data transfer processing between the transmission buffer register or reception buffer register and data memory according to the I10 request for transmission completion and reception completion, and data transfer processing for controlling the monitoring timer, are performed by a program. This is achieved without any intervention.

In this data transfer (hereinafter referred to as automatic data transfer), when an l109 request is generated from peripheral hardware, the CPU stops the current 10G2M interception operation and retains the CPU status (PC, PAW) and data. The CPU itself performs the data transfer process while the automatic data transfer process is continued, and when the CPU finishes the automatic data transfer process, it resumes execution of the interrupted program using the status and data that it held. Therefore, from the software, the interruption of 10 grams is not visible, and it appears as if automatic data transfer processing was automatically inserted during 10 grams processing.

In addition, as a monitoring timer, two hardware timers are not required, one for serial transmission and one for serial transmission, and the monitoring timer functions for serial transmission and serial reception can be set in memory, and these can be set in one timer. A method of control using individual hardware timers is used.

In this way, in the automatic data transfer processing equipped with the monitoring function of the present invention, by reducing the frequency of occurrence of transmission completion interrupts or reception completion interrupts, which are mainly performed by software processing, it is possible to suppress a decline in the processing capacity of the jcPTJ and to , one monitoring timer function required for each peripheral hardware.
The burden on the p1 timer is reduced by controlling it using two hardware timers.

(Example) FIG. 1 shows a block diagram of one embodiment of the invention.

In this embodiment, the serial data transfer device [1 includes transmission lines 61 . Transmit buffer register 11 and receive line 62. It has a reception buffer register 12, and also has a CT8y input 63 and a data line 64 as transmission/reception control signals.
5, outputs RxBF 66 and CTS notification signal 67. The timer 6 consists of a set of timer unit timers (0316 and decrementer 22).
316 is the timer 0 modulo register 18 and the timer 0
The timer register 19 outputs a timer count completion signal 69 to the r-/o request control section 31.

The I10 request control unit 31 has an I10 channel register having peripheral hardware address information for each peripheral hardware and a length-to-bus control register group 41 including a monitoring function enable bit color, and a transmission channel register 42 .
This includes a transmission monitoring function enable bit 43, a reception channel register 44, and a reception monitoring function enable bit 45.

The execution unit receives the I1010 process actual request line 71 and the 110 process execution mode designation fIM72 from the work 10 request control unit 31, and controls the operation of the execution unit.I10 request reception is performed by the unit 32.
Program memory for storing programs such as interrupt processing 10g4. Data memory 51 that holds the transmission/reception processing take PCL points to all addresses of the program to be executed next
3. Arithmetic and logic operation unit (hereinafter referred to as ALU) having an arithmetic and logic operation function 33. P indicates the operating status of the entire execution unit
8W14, a general-purpose register set 15 that holds the take being processed, an instruction register 34 that holds the next instruction to be executed, an instruction decoder 35 that decodes the contents of this instruction register 34 and generates various control signals, this instruction decoder 35
Execution control unit 3 that controls the operation of the entire execution unit based on the output of
6 p411 has been created. Furthermore, the execution unit includes the first . Second
It has an automatic transfer register group 37.38 with a monitoring function,
These automatic transfer register groups 37 and 38 with monitoring functions are
Monitoring timer module (hereinafter referred to as WDM) 46, 51 of the software monitoring timer mapped onto the memory
, monitoring timer counter unit (hereinafter referred to as WDC) 47.
8 F R that specifies the address of 52 and special register.
Pointer (hereinafter referred to as 8FRP) 48.53. Terminal counter that maintains the number of automatic data transfers (
(hereinafter referred to as TC) 49, 54, memory pointer (hereinafter referred to as MP) 50 that specifies the address of the data memory
55't-, and all these functional units are connected to the internal path 7.

Next, the operation of automatic data transfer processing with a monitoring function in serial transmission and reception will be explained.

The transmission l109N request process first uses the timer 0 modulo register 18 and the WDM 46 of the first automatic transfer register group 37 with a monitoring function in order to obtain a predetermined monitoring time interval (time from completion of transmission to completion of reception at the destination) t. Set the count value to . This predetermined monitoring time is expressed as the product of the count value of the timer 0 modulo register 18 and the count value of the WDM 46. The serial take transfer device 1 outputs TxBE65 to the I10 request control unit 31 when the send take in the send buffer register 11 becomes empty due to external transmission.

In response, the I10 request control unit 31 sends an I10 request reception request to the I1010 processing execution unit 32, I[ii! 71 and I10
Processing format designation 1Is72f: Output. 110 request reception unit 32 detects that I1010 process actual request line 71 is active, and at the same time 110 process execution form specification 11
When detecting that 172 is low level, l10IQ
The request reception unit 32 recognizes this I10 request as an interrupt process, and executes normal interrupt process with the PC13 and P8W14゜saving and restoring the general-purpose register set 15 ◇ On the other hand, the I1010 process actual specification 1172 is at the 71 level. If so, the I10 request reception unit 32 recognizes that the I10 request is an automatic data transfer request with a monitoring function, and sets its processing code in the instruction register 34.

The execution control unit 36 performs the next process while holding the values of PCl 3 , P8W14, and general-purpose register set 15. First, the %x10p request control unit 31 outputs the address of the first automatic transfer register group 37 with monitoring function to the transmission channel register 42 on the internal bus 7, and the execution control unit 36 reads this address and performs the first monitoring function. select automatic transfer register group 37. Next, the execution control unit 36 reads the transmission data from the transmission data storage area A pointed to by MP50 of the first automatic transfer register group 37 with monitoring function,
8 Transfer to the transmission buffer completion register 11 pointed to by FRP 48 and further transfer to the value t-WDC 47 of WDM 46 110 Service control register group 41 of request control unit 31
Set the transmission monitoring function enable bit 4:1rlJ in
Timer (0) 16 that controls the monitoring software timer
send a start signal to. MP using ALU33
5 Add "1" to the value of Q and store it in this MP50 again, subtract "1" from the value of TC49 and store it in TC49 again, and complete the automatic data transfer process.

Furthermore, when the value of TC49 becomes "0" after subtraction, it is assumed that the series of data transmission has been completed, and ■10g! The request control unit 31 reactivates the I10 processing request line 71 and also specifies the I10 processing type lfj! 72 is now set to low level to generate a transmission interrupt request and start the transmission interrupt program.

The timer (0116) outputs a timer count completion signal 69 to the I10 request control unit 31 at predetermined time intervals according to the value set in the timer 0 modifier register 18. The l1011i request control unit 31 activates the I10 process execution request line 71 and specifies the I10 process processing mode.
When i172 is set to high level, I10 request acceptance notifies unit 32 of timer 0 automatic data transfer processing.

The timer 0 automatic data transfer process is performed by the r10 request control unit 31.
And the execution control unit 36 executes a series of processes as shown below.

1) Service control register group 4 of I10 request control unit 31
The address information of the first channel register (in this case, the transmission channel register 42) in the internal bus 7 is outputted onto the internal bus 7.

2) The execution control unit 36 reads this address and selects the first automatic transfer register group with monitoring function 37L-%WD.
Subtract 1 from the value of C47 using ALU33t-.

3) Check the transmission monitoring function enable pit 43,
If this is "1", the subtraction result is stored in the WDC 47 again, and if it is "0", it is not stored.

(If ?-, the transmission monitoring function enable bit 43 is
1'', the value of the WDC 47 is decremented by 1. ) 4) The execution control unit 36 sends I10111 to the request control unit 31.
This I10 request control unit 3 notifies the end of the subtraction process.
1 transfers the address information of the next channel register to internal bus 7.
Output on top.

By repeating the series of processes 1) to 4) above, even though the monitoring function enable pit is "1", l101
Only the WDC of the request destination is decremented by 1. In addition, he completed a series of subtraction processes for all I10 locations,
When the value of a certain WDC becomes 0, the I10 request control unit 31 activates the I10 processing execution request #71t again, sets the I10 processing type designation line 72 to low level, and executes the timer 0 interrupt processing. to start.

When normal serial transmission is performed, the serial data transfer device 1 receives a reception completion notification from the other party within a predetermined time by activating the CT 863.

When CT86B becomes active, this serial data transfer device 1 sends a CT8 notification signal (67) tIlo and IQ request control unit 31, and this r10? The request control unit 31 receives the I10 request and sends the I10 process execution request I! to the unit 32! JCT8 automatic data transfer processing is carried out by activating 71 and setting the `I10 processing R included line 72 to high level. This sets the transmission monitoring function enable bit 43 in the service control register group 41 of the fi110 request control unit 31 to "0" to stop the subtraction of the WDC 47 by the timer 0 automatic data transfer process.

In addition, an error occurred in the serial transmission and the CT
If 863 does not become active, the WDC470 subtraction stop that performs CT8 automatic meter transfer processing is not performed, and the
As a result of the subtraction of DC47, the value ζ0WDC4'If) is rO
By starting the processing including timer 01111, the CPU can detect an abnormality in serial transmission.

Next, the reception I10 request will be explained.

Similar to the sending l10IJQ request process, the predetermined monitoring time interval (
In order to obtain the data reception interval), count values are set in advance in the timer 0 modulo register 18 and the WDM 52 of the automatic transfer register group 38 with monitoring function of @2. When the reception buffer register 12 becomes full, the serial data transfer device 1 sends a D8R64 signal to notify the destination of reception completion.
Activate and set RxBF66 to l1011a
output to the request control section 31. In response to this, the I/Qt request control unit 31 outputs an I10 process execution request line 71 and an I10 saturation execution mode designation [72t-] to the I10 request acceptance unit 32.

The I105 request reception section 32 sends the I10 processing execution request details 71
is active and samples the level of the I10 processing type designation line 72. If the level is low, the I10 request reception section 32 recognizes this I10 request as an interrupt processing, and the reception interrupt processing program is activated. .

When this I10 processing type designation line 72 is at a high level, the I10 request reception section 32 recognizes that this I10 IV request is an automatic data transfer request with a monitoring function, and sets the processing code in the instruction register 34. do. The execution control unit 36 starts the process described below while holding the values of PCI 3 , PSWI 4 , and general-purpose register set 15.

The I10 request control unit 31 outputs the address of the second automatic transfer register group 38 with a monitoring function onto the internal bus 7, and the execution control unit 36 reads this address and outputs the address of the second automatic transfer register group 38 with a monitoring function. Select.

Next, the execution control unit 36 reads the received data from the receive buffer register 12 pointed to by 8FRP53 of the second automatic transfer register group 38 with a monitoring function, transfers it to the received data storage area pointed to by MP55, and further transfers it to the received data storage area pointed to by MP55. After he transferred the value to the WDC 52, he asked: ■10 Set the reception monitoring function enable bit 45 in the service control register group 41 of the request control unit 31 to "1" and issue a tie? (Send a start signal to 0116. Then use ALU331-MP55
"1" is added to the value of TC54, "1" is subtracted from the value of TC54, and each is returned to end the automatic data transfer process.

At this time, when the value of TC54 becomes "0" by subtraction, it is assumed that a series of data reception has been completed, and the reception interrupt program is activated in the same way as at the time of transmission.

The timer (0316) which is restarted by the serial reception automatic data transfer process is output from the timer 0 modulo register.

In response to this, the I10 request control unit 31 activates the I10 processing request H71, sets the I10 processing type designation line 72 to high level, and notifies the I10 request reception unit 32 of timer 0 automatic data transfer processing. .

The timer 0 automatic data transfer process is similar to that described at the time of transmission.1109 Automatic data transfer register with monitoring function corresponding to the I10 request generation destination whose monitoring function enable bit in the service control register group 41 of the request control unit 31 is set to "1" All WDCs of the group are incremented by "1".

Regarding serial reception, the execution control unit 36 reads the address information of the reception channel register 44, selects the second automatic transfer register group 38t with a monitoring function, and selects the second automatic transfer register group 38t with a monitoring function.
The value 'fcALU 33 of 2 is used to decrement it by 1, and the result is returned to the WDC 52 again.

As in the case of sending, if the value of a certain WDC becomes 0 after completing a series of subtraction processing for all 1109 request destinations, I1
0 request control unit 31 activates the I10 processing execution request mV lt- again, and this time, the I10 processing processing format designation fj! 72 to low level to start timer 0 interrupt processing.

When serial reception is performed at normal time intervals, the WDC 52 is initialized each time data is received by automatic data transfer processing based on the reception l10-9 request.

However, if an abnormality occurs in the serial reception operation and the next data is not received within the normal time interval, the W
l) Since the value of C52 is not initialized, timer (0) 1
If the result of subtraction by the automatic data transfer process in step 6 is "0", the CPU can detect an abnormality in serial reception by activating the timer 0 interrupt.

(Effects of the Invention) As explained above, the information processing device according to the present invention includes two corresponding processing means, normal software interrupt processing and automatic data transfer processing with a monitoring function, in the generation of a transmission/reception I10 request. This can be selected by software.

In software interrupt processing, the processing required for serial transmission and reception is handled by interrupt service 14G as in the past, and in automatic data transfer processing with monitoring function, hardware is used for serial transmission and reception processing and processing associated with monitoring timer control. By reducing the frequency of software processing as much as possible, the CPU status (program counter)

The time spent on saving and restoring data, reading interrupt service instructions, decoding instructions, etc. can be significantly reduced.

In addition, by setting the monitoring timer function of each peripheral hardware in memory and controlling it with one hardware timer, the number of required hardware timers can be kept to a minimum, and data transfer processing with a monitoring function can be performed. Increased expandability of the number of possible peripheral hardware. Therefore, it is possible to perform pig transfer processing with a monitoring function that minimizes the reduction in CPU processing power and the burden on the timer, and has extremely high practical effects as an information processing device.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a microcomputer having a monitored automatic data transfer function according to an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional microcomputer. In the figure, 1... Serial data transfer device, 2... Interrupt control unit, 3... Execution unit, 4... 10g memory, 5... Data memory, 6... Timer, 7... Internal bus, 11... Transmission back completion register, 12...
Receive buffer register, 13...program counter, 14...10 gram status word, 15...
General-purpose register set, 16...Timer (03, 17,
...Timer 11+, 18...Timer 0 mojiro register, 19...Timer 0 timer register, 20...Timer 1 mojiro register, 21...Timer 1 tie i register, 22...Decrementer, 31 ...I10 request control section, 32...I10 request reception section, 33...A
LU, 34...instruction register, 35...instruction decoder, 36...execution control unit, 37.38...first. 2nd automatic transfer register with monitoring function, 41... Service control register group, 42... Transmission channel register,
43...Transmission monitoring enable pit, 44...Reception channel register, 45...Reception monitoring enable pit), 46°51...WDM% 47.52・WDCl
48.53...5FRP, 49,54...TC,
50,55...MPl 61...Transmission line, 62
...Reception line, 63---CTC, 64-=D8B
, 65-TxBE, 66-RxBF, 67...CT
8 notification line, 68... interrupt request line, 69... timer (
0) Count completion signal line, 70... Timer (1) Count completion signal line, 71... I10 process execution request line, 7
2... I10 processing processing type designation line, O

Claims (1)

[Claims] a serial data transfer device that generates a transmission processing request associated with transmission processing and a reception processing request associated with reception processing; a timer that generates a measurement completion processing request upon completion of time measurement; and a memory unit that stores transmitted and received data and programs; In an information processing device including a central processing unit (hereinafter abbreviated as CPU) that performs processing based on the transmission processing request, reception processing request, and measurement completion processing request, the processing is performed while maintaining the state of the CPU related to the program execution. Sending processing request,
The serial data transfer device includes data transfer processing means for performing data transfer processing corresponding to the reception processing request, and serial transmission/reception abnormality occurrence detection means based on the measurement completion processing request of the timer, and the serial data transfer device performs data transfer processing corresponding to the transmission processing request and reception processing. An information processing apparatus characterized in that, when a request is generated, the CPU performs transmission/reception data processing by the data transfer processing means and monitoring of the transmission/reception data processing by the serial transmission/reception abnormality detection means.