JPH01295352A - Data chain processing system - Google Patents

Abstract

PURPOSE:To control the frequent occurrence of data overrun faults when a peripheral control unit PCU executes a data chain DC function by considering not only the data transfer situation of the I/O bus side but that of the device side to detect the data overrun faults of the DC function. CONSTITUTION:In a PCU4 the data are transferred to a buffer 7 from an I/O bus control part 6 and a buffer input side counter 9 subtracts its count value by 1. When the data are transferred to a device transfer control part 8, a buffer output side counter 11 subtracts its count value by 1. When the count value of the counter 9 is equal to 0, a processor 14 gives an instruction to the counter 9 to set the next count value 41 via a buffer input side count register 10. If this setting operation is continued until the count value of the counter 11 is equal to 0, a DC action is continued as it is. Thus it is possible to control the frequent occurrence of the data overrun faults when the PCU4 executes the DC function.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data chain processing method, and more particularly to a data chain processing method for detecting and restoring a data overrun failure in an information processing system that supports a data chain function.

[Conventional technology]

The data chain function (hereinafter abbreviated as DC function) is a function to effectively utilize the resources of the main memory (hereinafter abbreviated as MM). For example, the /O0 byte data area on MM If you need , normally MM
An empty area with a size of /O0 bytes or more is required somewhere above, but in such a case, DCJa functions can store, for example, 50 bytes from address A, 20 bytes from address B, and 30 bytes from address C. In this way, it attempts to secure a data area of the required size by combining several empty areas. In this way, the vacant areas on the MM can be effectively utilized.

Conventionally, such a C function has been implemented, for example, through an MMIOI, a central processing unit (hereinafter abbreviated as cpu)/O2, MM/O1 and cpU/O2, and a memory bus 121 as shown in FIG. I/O (input/output) connected to
Processor (hereinafter abbreviated as IOP)/O3 and I
Peripheral control bag connected via OP/O3 and I/O interface 122! (hereinafter abbreviated as PCU)/O
In an information processing system consisting of a PCU/O4 and a device/O5 connected via a device interface 126, the information processing system is realized as one function of the l0P/O3.

However, in recent years, V L S T (Very L
largeScale integrated ci
Due to the miniaturization of devices such as by converting the I/O interface 122 into an I/O bus, as shown in FIG. There is a tendency to change to 123. As the rOP/O3 and PCU/O4 have a bus structure, it becomes possible for the PCU/O4 to become aware of the MMIOI address, albeit indirectly.
It will become possible to share some of the functions performed by O3. Under these circumstances, the DC function can be transferred to PCU/O4.
I've started to do this. In other words, the l0P/O3 has come to place emphasis on its role as a distribution device (D 1 tributor) from the MMIOI or CPU/O2 to each PCU/O4.

Here, an overview of the DC function performed in I OP /O3 will be explained. When the I OP /O3 receives a command (command #l) that instructs a data chain, it sends the following command (command #2) to the command #1.
When the data transfer specified by command #1 is completed, the next data transfer (specified by command #2) is read from M M /O1 before the execution of l is completed.
This means that when there is no more buffer space in the l0P/O3, the PCU/O4, which is a lower-level device,
Immediate response is required because it may lead to data overrun failure on the side. In order to prevent failures in the rOP/O3 from being reported to the PCU/O4, an overrun failure (command overrun failure or data In many cases, it is treated as a disability.

Even if the PCU/O4 performs the DC function, the idea behind the IOP/O3 is that if the preparation for command #2 is not completed when the execution of command #l is completed, it will be treated as an overrun failure. P CU /O as it is
Uke was inherited as a philosophy in 4. However, PCU
From the /O4 side, this means that more functions have been added than before, and with the existing processor performance, there is a possibility that the above-mentioned overrun failure where command #2 cannot be prepared in time when command #1 finishes execution may occur frequently. has arisen.

[Problem to be solved by the invention]

In the conventional data chain processing method described above, PCU/
When performing DCIm functions in O4, Uke inherited the concept of IOP/O3 as the definition of overrun failure, so there was a possibility that overrun failures would occur frequently in PCU2O5, which would lead to performance deterioration of PCU/O4. It has the disadvantage of being large.

By the way, data transfer between the PCU/O4 and the device/O5 often depends on the performance and operation of the device/O5, and its performance is generally inferior to the data transfer performance of the I/O bus 123. . Therefore, when the DC function is performed by the PCU/O4, the above-mentioned Even in the case of an overrun failure where command #2 cannot be prepared in time when command #1 finishes executing, the overrun failure can be immediately resolved by preparing command #2 before data transfer on the device/O5 side is completed. Obstacles can be avoided.

In view of the above-mentioned points, an object of the present invention is to detect a data overrun failure of the DCI function by taking into consideration not only the data transfer status on the summer/O bus side but also the data transfer status on the device side. An object of the present invention is to provide a data chain processing method capable of suppressing frequent data overrun failures when performing the following steps.

[Means to solve the problem]

The data chain processing method of the present invention is an information processing system that supports a data chain function, and is located between a ■/O processor and a device, and the ■/O processor is an I/O processor.
In a peripheral control device connected via a /O bus and connected to the device via a device interface, data transfer to and from the 1/O bus is performed using the I/O processor using the address of the main memory. to control 1
/O bus control unit and the above! a buffer that temporarily holds data from the I/O bus, a device transfer control unit that controls data transfer with the device, and a buffer input side counter that counts data input from the I/O bus to the buffer. , a buffer input side next count register that stores the next count value to be counted continuously when the count of this buffer input side counter runs out, and a buffer output side counter that counts the output of data from the buffer to the device. , a buffer output side next count register that stores the next count value to be counted continuously when the count of this buffer output side counter runs out; a count 0 notification of the buffer input side counter and the buffer output side counter; a data overrun detection unit that outputs a next count value set request, a count over notification, and a data overrun failure notification in response to the next count value valid signal of the buffer input side next count register and the buffer output side next count register; and a processor that receives the next count value set request from the detection unit, the count over notification, and the data overrun failure notification, and performs data chain processing and data overrun failure recovery processing.

[Effect]

In the data chain processing method of the present invention, the I/O bus control unit controls data transfer to and from the I/O bus via the I/O processor, with the address of the main memory device in mind, and the buffer The device transfer control unit controls data transfer with the device, the buffer input side counter counts the input of data from the I/O bus to the buffer, and the buffer input side next count register stores the next count value to continue counting when the counter on the buffer input side runs out, the counter on the buffer output side counts the output of data from the buffer to the device, and the next count register on the buffer output side stores the next count value to continue counting when the counter on the buffer input side runs out. When the count of the counter on the side counter runs out, the next count (direction) to be counted continuously is stored, and the data overrun detection unit sends the count O notification of the counter on the buffer input side and the counter on the buffer output side, and the next count register on the buffer input side and the buffer output. Upon receiving the next count value valid signal of the side next count register, the processor outputs the next count value set request, count over notification, and data overrun failure notification, and the processor outputs the next count value set request, count over notification, and data overrun failure notification from the data overrun detection section. Upon receiving the data overrun failure notification, data chain processing and data overrun failure recovery processing are performed.

〔Example〕

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an information processing system to which a data chain processing method according to an embodiment of the present invention is applied. This information processing system consists of MMI and CPU2.
, l0P3 connected to MMI and CPU2 via memory bus 21, PCO2 connected to l0P3 via I/O bus 22, and device 5 connected to PCtJ4 via device interface 26, Its main parts are composed of:

The PCO 2 includes: ■ an I/O bus control jB unit 6 connected to the /O bus 22 and a data bus 23; a buffer 7 connected to the I/O bus control unit 6 and a data bus 24;
A device transfer control unit 8 connected to the buffer 7 via the data bus 25 and also connected to the device interface 26, a buffer input side counter 9 that receives data input notification 31 from the buffer 7 and counts (subtracts); A buffer input side next count register /O that stores the next count value 41 to be counted continuously when the count of the input side counter 9 is exhausted, and a buffer output that counts (subtracts) upon receiving the data output notification 32 from the buffer 7. side counter 11 and buffer output side counter 1
A buffer output side next count register 12 that stores the next count value 42 to be counted continuously when the count value 1 is exhausted, and a buffer input side next count register /O
The next count value valid signal 51 from the buffer input side counter 9, the count 0 notification 52 from the buffer input side counter 9. In response to the count 0 notification 53 from the buffer 1 output side counter 11 and the next count value valid signal 54 from the buffer output side next count register 12, a next count value set request 61. Count over notification 62゜ Data overrun detection unit 13 that outputs data overrun failure notification 63 and next count value set request 64, and next count value set request 61 that is controlled by firmware and output from data overrun detection unit 13. Countover notification 62. The processor 14 receives the data overrun failure notification 63 and the next count value set request 64 and performs data chain processing and data overrun failure recovery processing.

The buffer 7 is connected to the data bus 24 from the I/O bus control unit 6.
Data entry notification 31 every time data is transferred via
, and outputs a data output notification 32 every time data is transferred to the device transfer control unit 8 via the data bus 25.

The buffer input end counter 9 counts (subtracts) the next count (a41) set from the buffer input side next count register/O every time the data manual notification 31 is output from the buffer 7, and when the count value becomes 0. Count 0
A notification 52 is output.

The buffer input side next count register lO makes the next count value valid signal 51 active while the valid next count value 41 is stored by the processor 14, and when the count value of the buffer input side counter 9 becomes 0, the next count is started. At the same time as setting the value 41 in the buffer input end counter 9, the next count value valid signal 51 is made inactive.

The buffer output side counter 11 counts (subtracts) the next count value 42 set from the buffer output side next count register 12 every time the data output notification 32 is output from the buffer 7, and when the count value reaches 0, the count becomes 0.
A notification 53 is output.

The buffer output side next count register 12 makes the next count value valid signal 54 active while the valid next count value 42 is stored by the processor 14, and when the count value of the buffer output side counter 11 becomes O, it starts the next count. At the same time as setting the value 42 in the buffer output side counter 11, the next count value valid signal 54 is made inactive.

Next, the operation of the data chain processing system of this embodiment configured as described above will be explained.

Data is now transferred from the MMI to the memory bus 21. [OF2
．． I/O bus 22. Data J': S23. T/
Q Lotus control unit 6. Data bus 24. Buffer 7, data bus 25. It is assumed that the data is transferred to the device 5 via the device transfer control unit 8 and the device interface 26.

At the beginning of a data chain operation, processor 14:
Based on the first command instructing the data chain, the next count values 41 and 42 are sent to the buffer input side counter 9 and buffer output side counter 11 through the buffer input side next count register /O and the buffer output side next count register 12, respectively. settings, and operate the I/O bus control unit 6 and device transfer control unit 8, respectively.

When data is transferred from the I/O bus control unit 5 to the buffer 6 via the data bus 24, a data input notification 31 is output from the buffer 6 to the buffer input side counter 9, and the buffer input side counter 9 receives the count value. One count (
subtraction).

Similarly, when data is transferred from the buffer 6 to the device transfer control unit 8 via the data bus 25, a data output notification 32 is output from the buffer 6 to the buffer output side counter 11, and the buffer output side counter 11 Count (subtract) the count value by one.

If the next count value valid signal 51 indicating that a valid next count value 41 is stored in the buffer input side next count register /O does not become active while the buffer input side counter 9 is operating, the data overrun detection unit 13
outputs the next count value set request 61 to the next count register/O on the buffer input side and notifies the processor 14. Upon receiving the eighth count value set request 61, the processor 14 sets the next count value 41 based on the next command. is stored in the next count register /O on the buffer input side. Therefore, the next count value valid signal 51 from the next count register /O on the buffer input side becomes active, and the data overrun detection section 13 stops outputting the next count value set request 61.

Similarly, while the buffer output side counter 11 is operating, if the next count valid signal 54 indicating that a valid next count value 42 is stored in the buffer output side next count register 12 does not become active, the data The overrun detection unit 13 outputs a next count value set request 64 to the buffer output side next count register 12 and notifies the processor 14 .

The processor 14 that receives the next count value set request 64 stores the next count value 42 based on the next command in the next count register 12 on the buffer output side. Therefore, the next count value valid signal 54 from the buffer output side next count register 12 becomes active, and the data overrun detection section 13 stops outputting the next count value set request 64.

In such a state, for example, when the count value of the buffer input side counter 9 becomes 0, the buffer input side counter 9 activates the count O notification 52 and notifies the data overrun detection unit 13.

At this point, the data transfer performance to the device 5 is usually inferior to the data transfer performance of the I/O bus 22, so
The count value of the buffer output side counter 11 that counts data transfer to the device 5 should not yet reach 0. Therefore, in such a case, the data overrun detection unit 13 immediately outputs a count over notification 62 to notify the processor 14 of the count over. Upon receiving this count over notification 62, the processor 14 causes the buffer input side counter 9 to set the next count value 41 from the buffer input side count register IO.

If the next count value 41 is set before the count value of the buffer output side counter 11 reaches 0, the count O notification 52 from the buffer input side counter 9 is immediately canceled and the data chain operation continues as it is. , data overrun failure is avoided.

However, if the next count value 41 is not set in time by the processor 14 to the buffer input side counter 9 and the count value of the buffer output side counter 11 becomes 0, the buffer output side counter 11 sends a count 0 notification 53. The data overrun detection unit 13 that outputs the count O notifications 52 and 53 at the same time outputs a data overrun failure notification 63 as a data overrun failure, and notifies the processor 14 of the data overrun failure notification 63. This data overrun failure notification 6
3, the processor 14 performs data overrun failure recovery processing.

〔Effect of the invention〕

As explained above, the present invention detects data overrun failures in the DC function by taking into account not only the data transfer status on the I/O bus side but also the data transfer status on the device side. This has the effect of suppressing frequent data overrun failures.

[Brief explanation of the drawing]

Fig. 1 is a blank diagram showing the configuration of an information processing system to which a data chain processing method according to an embodiment of the present invention is applied, and Fig. 2 is an example of an information processing system to which a conventional data chain processing method is applied. FIG. 3 is a block diagram showing another example of an information processing system to which the conventional data chain processing method is applied. In the figure, 1...MM. 2...CPU. 3...IOP. 4...pcu. 5... Device, 6... I/O bus control unit, 7... Buffer, 8... Device transfer control unit, 9... Buffer input side counter, /O... Buffer input side next Count register, 11.
...Buffer output side counter, 12...Buffer output side next count register, 13.
. . . Data overrun detection unit, 14 . . . Processor, 21 . , 32...Data output notification, 41, 42-Next count value, 51, 54-Next count value valid signal, 52, 53-Count 0 notification, 61, 64-Next count value set request, 62...Count Over notification, 63...Data overrun failure notification.

Claims (1)

[Scope of Claims] An information processing system supporting a data chain function, wherein the I/O processor is located between an I/O processor and a device;
In a peripheral control unit connected to the processor via an I/O bus and to the device via a device interface, data transfer with the I/O bus is performed via the I/O processor to the main memory. an I/O bus control unit that controls the address of the I/O bus; a buffer that temporarily holds data from the I/O bus; a device transfer control unit that controls data transfer with the device; a buffer input side counter that counts the input of data from the /O bus to the buffer; and a buffer input side next count register that stores the next count value to be counted continuously when the count of this buffer input side counter runs out. , a buffer output side counter that counts the output of data from the buffer to the device, and a buffer output side next count register that stores the next count value to be counted continuously when the count of the buffer output side counter is exhausted. , upon receiving the count 0 notification of the buffer input side counter and the buffer output side counter and the next count value valid signal of the buffer input side next count register and the buffer output side next count register, a next count value set request is made, and the count is over. a data overrun detection unit that outputs a notification and a data overrun failure notification; and data chain processing and data overrun failure recovery in response to the next count value set request, the count over notification, and the data overrun failure notification from the data overrun detection unit. A data chain processing method comprising: a processor that performs processing;