JPH04147347A - Processor failure recovery control method - Google Patents

Abstract

PURPOSE:To execute failure recovery processing efficiently and appropriately when a processor failure occurs in a slave processor by controlling the processor failure recovery processing using the value of a parallel execution counter. CONSTITUTION:Master processor 1, when a failure occurs in a slave processor 2, compares a parallel execution counter 11 with a parallel execution allowable number 16 obtained by looking up a parallel execution control table 13 using a CPU activity ratio information 12 calculated by a CPU activity ratio function 31. As a result of the comparison, if the value of the parallel execution counter 11 is within the parallel execution allowable number 16, the master processor 1 starts failure recovery processing 7 onto a slave processor 2 through a processor bus 5. When the value of parallel execution counter 11 exceeds the parallel execution allowable number 16, the master processor waits unit the processor failure recovery processing 7 starts. After the recovery processing starts, the master processor sends an inter-instruction signal sending timing 21 to the slave processor.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a multiprocessor system such as an electronic exchange or a data communication system in which a master processor and a plurality of slave processors are connected by a processor bus. This paper relates to a processor failure recovery control method in a system in which it is not allowed to interrupt services.

[Conventional technology]

Conventionally, processor failure recovery control methods in this type of multiprocessor system have involved unconditionally executing a certain number of processor failure recovery processes in parallel for multiple failed slave processors, or A certain timing delay was always required when sending a series of instruction signals to slave processors.

[Problems to be Solved by the Invention] As mentioned above, in the conventional processor failure recovery control method in a multiprocessor system, a constant number of processor failure recovery processes are executed in parallel, and a master processor to slave There is always a certain timing delay when sending a series of instruction signals to the processor, so if a processor failure occurs in a slave processor and the system is already under a high load, it will be difficult to recover from the processor failure. When a high load state becomes redundant due to the start of processing, or when the system is in a low load state, the processing time for recovering from a processor failure cannot be shortened to a certain amount of time even if the system processing capacity is available, and the processor failure may occur. There are drawbacks such as the inability to perform recovery processing efficiently.

An object of the present invention is to efficiently and appropriately control processor failure recovery processing without adversely affecting system operation, regardless of the level of system load when a processor failure occurs in a slave processor. The objective is to provide a recovery control method.

[Means to solve the problem]

The processor failure recovery control method of the present invention is a processor failure recovery control method in a multiprocessor system in which a master processor equipped with a main storage device and a plurality of slave processors are connected by a processor bus.
The main storage includes a parallel execution counter that indicates the number of processor failure recovery processes being executed in parallel, a CPU usage rate function that periodically calculates the CPU usage rate of the master processor, and a CPU usage rate function that calculates the CPU usage rate of the master processor. a parallel execution control table that stores a permissible number of parallel executions of processor failure recovery processing indexed by the CPU usage rate information; and an instruction from the master processor to the slave processor. A time measurement function that measures the time from the time of signal transmission to the time of reception of a response signal from the slave processor to the master processor, response time information that stores the time measured by the time-side quantitative number, and based on the response time information. It has a transmission timing control table that stores indexed transmission timing between instruction signals from the master processor to the slave processor, and a timing function that takes an arbitrary timing delay, and when a processor failure occurs in the slave processor, , when the parallel execution counter is within the permissible number of parallel executions in the parallel execution control table indexed by the CPU usage information, start processor failure recovery processing for the slave processor, and increase the permissible number of parallel executions. When the time limit is exceeded, wait for the start of the processor failure recovery process, and after the start of the processor failure recovery process, use the response time information when transmitting an instruction signal from the master processor to the slave processor in the processor failure recovery process. The configuration is such that the transmission timing between the instruction signals in the indexed transmission timing control table is transmitted after a timing delay is taken by the timing function.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a diagram showing an example of the configuration of a multiprocessor system according to the present invention, in which a master processor 1 and slave processors 2, 3, and 4 are connected by a processor bus 5, and the master processor 1 is equipped with a main memory 6. . Master processor 1 has slave processors 2, 3 .
When a processor failure occurs in slave processor 4, failure recovery of slave processors 2 and 3.4 is controlled by processor failure recovery processing 7 and 8.9 through processor bus 5.

FIG. 2 is a diagram showing an example of control information and processing functions stored in the main memory shown in FIG. 1. In FIG. 2, in the main memory 6, there is a parallel execution counter]1 that indicates the number of processor failure recovery processes currently being executed in parallel, and a counter C that periodically calculates the CPU usage rate of the master processor 1.
A PU usage rate function 31, CPU usage rate information 12 that stores the calculated CPU usage rate, and the CPU usage rate information 12.
Parallel execution control table 13 that stores the number of parallel executions allowed for processor failure recovery processing indexed by 14, 15, and 16
and slave processor 2.3 from master processor 1.
．． 4, the slave processor 2
, 3.4, a time measurement function 32 that measures the time until the response signal is received to the master processor 1, response time information 17 that stores the measured time, and response time information 17.
Transmission timing 19 between instruction signals from master processor 1 to slave processors 2, 3.4 indexed by
, 20.21;
It has a timing function 33 that takes an arbitrary timing delay.

Next, as a specific example, the operation when a failure occurs in the slave processor 2 will be described. When a processor failure occurs in the slave processor 2, the master processor 1 calculates the parallel execution counter 11 and the CPU usage rate function 3.
The CPU utilization information 12 calculated and stored in step 1 is compared with the permissible number of parallel executions 16 obtained by indexing the parallel execution control table 13, and when the parallel execution counter 11 is within the permissible number of parallel executions 16, the processor bus 5, the processor failure recovery process 7 of the slave processor 2/\ is started, and when the parallel execution counter 11 exceeds the parallel execution allowable number 16, the processor failure recovery process 7 is started.

After the processor failure recovery process 7 is started, the time measurement function 3 is used when transmitting an instruction signal from the master processor 1 to the slave processor 2 in the processor failure recovery process 7
The inter-instruction signal transmission timing 21 obtained by indexing the transmission timing control table 18 using the response time information 17 measured and stored in step 2 is transmitted after a timing delay is taken by the timing function 33. Regarding a series of instruction signal transmission and response signal reception in processor failure recovery processing 7, the above procedure is repeatedly executed.

Next, with reference to FIG. 3, an example of how to determine (concept) the value of the instruction signal inter-transmission timing 21 will be described. FIG. 3 is a diagram showing an example of the transmission timing control table 18 and specific values of the instruction signal inter-transmission timing 21 stored therein. It is shown. Response time information is 50 rn s
If it is within 51m5, the next instruction signal will be sent without timing delay, and if it is between 51m5 and 100m5,
Send the next instruction signal after taking a timing delay of 25m5, and if the distance is between 101m5 and 150m5, 50m5
After taking the timing delay of m5, the next instruction signal is transmitted. Similarly, the next instruction signal is transmitted after a predetermined inter-instruction signal transmission timing has been established in accordance with the value of the response time information.

〔Effect of the invention〕

As explained above, in the present invention, when a processor failure occurs in a slave processor, the parallel execution counter
When the number of parallel executions is within the permissible number of parallel executions in the parallel execution control table indexed by the PU usage information, the processor failure recovery process for the slave processor is started, and when the permissible number of parallel executions is exceeded, the processor failure recovery process is started. After waiting and starting the processor failure recovery process, when the master processor sends an instruction signal to the slave processor in the processor failure recovery process, the transmission timing function between the instruction signals in the transmission timing control table indexed by the response time information is used. By transmitting the data after a timing delay, it is possible to efficiently and appropriately control the processor failure recovery processing without adversely affecting system operation, regardless of the level of system load when a processor failure occurs in a slave processor. It has the effect of being able to.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of the configuration of a multiprocessor system according to the present invention, and FIG. 2 is a diagram showing an example of the control information and processing functions stored in the main memory shown in FIG.
FIG. 3 is a diagram showing an example of a transmission timing control table and the transmission timing between instruction signals stored therein. 1... Master processor, 2,3.4... Slave processor, 5... Processor bus, 6... Main memory, 11... Parallel execution counter, 12... CP
U usage rate information, 13... Parallel execution control table, 14, 15
゜16... Permissible number of parallel executions, 17... Response time information, 18... Transmission timing control table, 19, 20.21
... Transmission timing between instruction signals, 31... CPU usage rate function, 32... Time measurement function, 33... Timing function.

Claims (1)

[Scope of Claims] In a processor failure recovery control method in a multiprocessor system in which a master processor equipped with a main memory and a plurality of slave processors are connected by a processor bus, a processor failure recovery process is performed in the main memory. A parallel execution counter that indicates the number of parallel executions, and a CPU that periodically calculates the CPU usage rate of the master processor.
A usage rate function, CPU usage information that stores the CPU usage rate calculated by the CPU usage rate function, and a parallel execution control table that stores the permissible number of parallel executions of processor failure recovery processing indexed by the CPU usage rate information. and a time measurement function that measures the time from the time when the master processor sends an instruction signal to the slave processor until the time when a response signal is received from the slave processor to the master processor.
response time information that stores the time measured by the time measurement function; a transmission timing control table that stores the transmission timing between instruction signals from the master processor to the slave processor indexed by the response time information; and an arbitrary timing. and a timing function that takes a delay, and when a processor failure occurs in the slave processor, the parallel execution counter is within the permissible number of parallel executions in the parallel execution control table indexed by the CPU usage information. Sometimes, a processor failure recovery process is started for the slave processor, and when the permissible number of parallel executions is exceeded, the start of the processor failure recovery process is waited for, and after the start of the processor failure recovery process, the processor failure recovery process is started. When transmitting an instruction signal from the master processor to the slave processor in processing, the transmission timing between the instruction signals in the transmission timing control table indexed by the response time information is transmitted after a timing delay is taken by the timing function. A processor failure recovery control method characterized by: