JPS6164673U - - Google Patents
Info
- Publication number
- JPS6164673U JPS6164673U JP13187884U JP13187884U JPS6164673U JP S6164673 U JPS6164673 U JP S6164673U JP 13187884 U JP13187884 U JP 13187884U JP 13187884 U JP13187884 U JP 13187884U JP S6164673 U JPS6164673 U JP S6164673U
- Authority
- JP
- Japan
- Prior art keywords
- output signal
- level
- logic
- delayed
- magnetic recording
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000012850 discrimination method Methods 0.000 claims description 2
- 238000006243 chemical reaction Methods 0.000 claims 2
- 230000003111 delayed effect Effects 0.000 claims 2
- 238000001514 detection method Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Digital Magnetic Recording (AREA)
- Signal Processing For Digital Recording And Reproducing (AREA)
Description
第１図は本考案のブロツク図である。第２図は
本考案の実施例を示す図である。第３図は本考案
の実施例の波形説明図である。第４図は従来の位
相弁別方式による再生系のブロツク図である。
FIG. 1 is a block diagram of the present invention. FIG. 2 is a diagram showing an embodiment of the present invention. FIG. 3 is a waveform explanatory diagram of an embodiment of the present invention. FIG. 4 is a block diagram of a reproduction system using a conventional phase discrimination method.
Claims (1)
気記録再生装置において、ゼロクロス検出回路が
、ＥＣＬ（Emitter Coupled Logic）のライン
レシーバで構成され、該ラインレシーバの出力信
号が、該出力信号の論理レベルをＴＴＬ（Transi
stor Transistor Logic）レベルに変換する論
理レベル変換回路と、該出力信号の変化点でＴＴ
Ｌレベルのパルスを発生するパルス発生回路とに
入力され、該パルス発生回路の出力信号が遅延さ
れて、遅延された該出力信号が前記論理レベル変
換回路の出力信号をラツチすることを特徴とする
磁気記録再生装置。 In a magnetic recording/reproducing device that reads recorded information using a phase discrimination method, a zero-cross detection circuit is composed of an ECL (Emitter Coupled Logic) line receiver, and the output signal of the line receiver determines the logic level of the output signal from TTL. (Transi
stor Transistor Logic) level, and a logic level conversion circuit that converts the output signal to TT level at the change point of the output signal.
The output signal is input to a pulse generation circuit that generates L-level pulses, the output signal of the pulse generation circuit is delayed, and the delayed output signal latches the output signal of the logic level conversion circuit. Magnetic recording and reproducing device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13187884U JPS6164673U (en) | 1984-08-30 | 1984-08-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13187884U JPS6164673U (en) | 1984-08-30 | 1984-08-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6164673U true JPS6164673U (en) | 1986-05-02 |
Family
ID=30690450
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13187884U Pending JPS6164673U (en) | 1984-08-30 | 1984-08-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6164673U (en) |
-
1984
- 1984-08-30 JP JP13187884U patent/JPS6164673U/ja active Pending
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