JPS6456030U - - Google Patents
Info
- Publication number
- JPS6456030U JPS6456030U JP15070687U JP15070687U JPS6456030U JP S6456030 U JPS6456030 U JP S6456030U JP 15070687 U JP15070687 U JP 15070687U JP 15070687 U JP15070687 U JP 15070687U JP S6456030 U JPS6456030 U JP S6456030U
- Authority
- JP
- Japan
- Prior art keywords
- control signal
- recording control
- synchronization
- outputs
- ratio
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 2
- 230000000630 rising effect Effects 0.000 claims 3
- 238000010586 diagram Methods 0.000 description 5
- 239000003990 capacitor Substances 0.000 description 1
Description
第１図は本考案の第１の実施例を示すブロツク
図、第２図は第１図に示された実施例の動作を説
明するための各部信号の波形図、第３図は本考案
の第２の実施例を示すブロツク図、第４図は第３
図に示された実施例の動作を説明するための各部
信号の波形図である。
１……サーボ系、２，２ａ……コントロール信
号発生部、３……データタイミング発生部、４，
４ａ……切換部、５……ＣＴＬヘツド、２１……
ＲＯＭ部、２２……インバータ、４１……ＡＮＤ
ゲート、４２……ＯＲゲート、４３……増幅器、
Ｃ１，Ｃ２……コンデンサ、Ｒ１……抵抗。
Fig. 1 is a block diagram showing the first embodiment of the present invention, Fig. 2 is a waveform diagram of signals of various parts to explain the operation of the embodiment shown in Fig. 1, and Fig. 3 is a block diagram showing the first embodiment of the present invention. A block diagram showing the second embodiment, FIG.
FIG. 4 is a waveform diagram of signals of various parts for explaining the operation of the embodiment shown in the figure. 1... Servo system, 2, 2a... Control signal generation section, 3... Data timing generation section, 4,
4a...Switching unit, 5...CTL head, 21...
ROM section, 22...Inverter, 41...AND
gate, 42...OR gate, 43...amplifier,
C 1 , C 2 ... Capacitor, R 1 ... Resistor.
Claims (1)
期間の比が６０対４０で論理値“１”をもちビデ
オテープのコントロールトラツク上に記録される
第１の記録コントロール信号の立上りに同期して
立上り、高レベル及び低レベルの期間の比が２７
．５対７２．５で論理値“０”をもつ第２の記録
コントロール信号を発生するコントロール信号発
生部と、前記コントロールトラツク上に記録しよ
うとするデータと記録指示信号とを入力し前記第
１の記録コントロール信号の立上りに同期して前
記データに対応した２値信号を出力するデータタ
イミング発生部と、このデータタイミング発生部
の出力信号に応じて前記第１及び第２の記録コン
トロール信号のうちの１つを出力する切換部とを
有することを特徴とする記録コントロール信号生
成回路。 Rising in synchronization with the rising edge of a first recording control signal outputted from the servo system and recorded on the control track of the videotape, having a logic value "1" with a ratio of high level and low level periods of 60:40, The ratio of high-level and low-level periods is 27
．． a control signal generating section that generates a second recording control signal having a logical value of "0" in a ratio of 5 to 72.5; a data timing generation section that outputs a binary signal corresponding to the data in synchronization with the rising edge of the recording control signal; and a data timing generation section that outputs a binary signal corresponding to the data in synchronization with the rise of the recording control signal; A recording control signal generation circuit comprising: a switching section that outputs one signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15070687U JPS6456030U (en) | 1987-09-30 | 1987-09-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15070687U JPS6456030U (en) | 1987-09-30 | 1987-09-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6456030U true JPS6456030U (en) | 1989-04-06 |
Family
ID=31424088
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15070687U Pending JPS6456030U (en) | 1987-09-30 | 1987-09-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6456030U (en) |
-
1987
- 1987-09-30 JP JP15070687U patent/JPS6456030U/ja active Pending
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