JPS6161850U - - Google Patents
Info
- Publication number
- JPS6161850U JPS6161850U JP1984145272U JP14527284U JPS6161850U JP S6161850 U JPS6161850 U JP S6161850U JP 1984145272 U JP1984145272 U JP 1984145272U JP 14527284 U JP14527284 U JP 14527284U JP S6161850 U JPS6161850 U JP S6161850U
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- semiconductor light
- emitting element
- output terminal
- input terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 4
Description
第１図は従来フオトカプラにＬＥＤを接続した
回路図、第２図は本考案の一実施例の斜視図、第
３図は第２図に示す一実施例の回路図、第４図は
本発明の他の実施例の回路図である。
１，１′，１″……ＬＥＤ、２……ホトカツプ
ラー、６……レシーバー用ホトカツプラー、１０
……レシーバー用集積回路、１１……出力ドライ
ブ用集積回路、１２，１２′……ＩＣ、Ｒ，Ｒ′
，Ｒ″……抵抗。
Fig. 1 is a circuit diagram of an LED connected to a conventional photocoupler, Fig. 2 is a perspective view of an embodiment of the present invention, Fig. 3 is a circuit diagram of an embodiment shown in Fig. 2, and Fig. 4 is a circuit diagram of an embodiment of the present invention. FIG. 3 is a circuit diagram of another embodiment of the invention. 1, 1', 1''...LED, 2...Photo coupler, 6...Photo coupler for receiver, 10
...Receiver integrated circuit, 11...Output drive integrated circuit, 12, 12'...IC, R, R'
,R″...Resistance.
Claims (1)
ンターフエース用集積回路において、外装表面上
に半導体発光素子が設けられ、この半導体発光素
子と電流制限用抵抗素子の直列回路の一端が前記
入力端子または前記出力端子に接続され、他端が
電源に接続されたことを特徴とするインターフエ
ース用集積回路。 In an interface integrated circuit equipped with an input terminal and an output terminal for transmitting a signal, a semiconductor light-emitting element is provided on the exterior surface, and one end of a series circuit of the semiconductor light-emitting element and a current-limiting resistance element is connected to the input terminal or the An integrated circuit for an interface, characterized in that it is connected to an output terminal and the other end is connected to a power supply.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1984145272U JPS6161850U (en) | 1984-09-26 | 1984-09-26 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1984145272U JPS6161850U (en) | 1984-09-26 | 1984-09-26 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6161850U true JPS6161850U (en) | 1986-04-25 |
Family
ID=30703527
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1984145272U Pending JPS6161850U (en) | 1984-09-26 | 1984-09-26 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6161850U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5130470B1 (en) * | 1962-10-03 | 1976-09-01 |
-
1984
- 1984-09-26 JP JP1984145272U patent/JPS6161850U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5130470B1 (en) * | 1962-10-03 | 1976-09-01 |
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