JPS6161547B2 - - Google Patents

Info

Publication number
JPS6161547B2
JPS6161547B2 JP6024880A JP6024880A JPS6161547B2 JP S6161547 B2 JPS6161547 B2 JP S6161547B2 JP 6024880 A JP6024880 A JP 6024880A JP 6024880 A JP6024880 A JP 6024880A JP S6161547 B2 JPS6161547 B2 JP S6161547B2
Authority
JP
Japan
Prior art keywords
semiconductor substrate
compound semiconductor
insulating film
gas
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP6024880A
Other languages
Japanese (ja)
Other versions
JPS56157063A (en
Inventor
Masamichi Okamura
Takeshi Kobayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP6024880A priority Critical patent/JPS56157063A/en
Publication of JPS56157063A publication Critical patent/JPS56157063A/en
Publication of JPS6161547B2 publication Critical patent/JPS6161547B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Bipolar Transistors (AREA)
  • Drying Of Semiconductors (AREA)

Description

【発明の詳細な説明】 本発明は化合物半導体基板を用いたMIS型半導
体装置の製法の改良に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in the manufacturing method of an MIS type semiconductor device using a compound semiconductor substrate.

近時、InP,GaAs,GaInAsP等でなる化合物
半導体基板を用いたMIS型半導体装置が着目され
ている。この様な化合物半導体基板を用いたMIS
型半導体装置の製法に於ては、化合物半導体基板
の表面上に絶縁膜を形成する工程を含むものであ
るが、一般に化合物半導体基板はその表面が空気
中の酸素によつても非常に酸化し易いものであ
る。
Recently, MIS type semiconductor devices using compound semiconductor substrates made of InP, GaAs, GaInAsP, etc. have been attracting attention. MIS using such a compound semiconductor substrate
The manufacturing method for type semiconductor devices includes the step of forming an insulating film on the surface of a compound semiconductor substrate, but in general, the surface of compound semiconductor substrates is very easily oxidized by oxygen in the air. It is.

この為、従来、化合物半導体基板を用いたMIS
型半導体装置の製法に於て含む化合物半導体基板
の表面上に絶縁膜を形成する工程として、塩酸液
等のエツチヤントを用いた化学エツチングにより
化合物半導体基板にその材料による新たな表面を
得、次にその新たな表面を得た化合物半導体基板
を反応炉内に配し、然る后その反応炉内に絶縁膜
形成用ガスを供給してその絶縁膜形成用ガスを用
いたCVD法により化合物半導体基板の新たな表
面上に絶縁膜を形成するという工程を採るとい
う、MIS型半導体装置の製法が提案されている。
For this reason, conventional MIS using compound semiconductor substrates
As a step of forming an insulating film on the surface of a compound semiconductor substrate, which is included in the manufacturing method of a type semiconductor device, a new surface of the material is obtained on the compound semiconductor substrate by chemical etching using an etchant such as a hydrochloric acid solution, and then The compound semiconductor substrate with the new surface is placed in a reactor, and then an insulating film forming gas is supplied into the reactor and the compound semiconductor substrate is processed by CVD using the insulating film forming gas. A manufacturing method for MIS type semiconductor devices has been proposed that involves forming an insulating film on a new surface of the semiconductor device.

然し乍ら斯る従来のMIS型半導体装置の製法の
場合は、それが含む化合物半導体基板の表面上に
絶縁膜を形成する工程に於ける、化学エツチング
により化合物半導体基板にその材料による新たな
表面を得て后、その新たな表面を得た化合物半導
体基板を反応炉内に配する迄の間に於て、更には
新たな表面を得た化合物半導体基板を反応炉内に
配して后、その化合物半導体基板の新たな表面上
にCVD法によつて絶縁膜を形成する迄の間に於
て、化合物半導体基板の新たな表面が空気に触れ
る懽れを有し、而して斯く化合物半導体基板の新
たな表面が空気に触れれば、化合物半導体基板の
表面上の絶縁膜が化合物半導体基板の材料の種々
の形での酸化物の複合体でなる表面層を介して形
成されるものである。即ち、今化合物半導体基板
がInPでなるものとし、又そのInPである化合物
半導体基板の新たな表面上にAl2O3である絶縁膜
を形成する場合で例示すれば、第1図に示す如く
InP基板でなる化合物半導体基板1の表面上の
Al2O3でなる絶縁膜2が、Inの種々の形の酸化
物、Pの種々の形の酸化物等の複合体でなる表面
層3を介して形成されるものである。
However, in the case of the conventional manufacturing method of MIS type semiconductor devices, in the process of forming an insulating film on the surface of the compound semiconductor substrate, chemical etching is used to create a new surface on the compound semiconductor substrate using the material. After that, before placing the compound semiconductor substrate with the new surface in the reactor, and after placing the compound semiconductor substrate with the new surface in the reactor, the compound semiconductor substrate with the new surface is placed in the reactor. Until the insulating film is formed on the new surface of the semiconductor substrate by the CVD method, the new surface of the compound semiconductor substrate is exposed to air. When the new surface is exposed to air, an insulating film on the surface of the compound semiconductor substrate is formed through a surface layer consisting of a composite of oxides of various forms of the material of the compound semiconductor substrate. That is, if we assume that the compound semiconductor substrate is made of InP and an insulating film of Al 2 O 3 is to be formed on a new surface of the compound semiconductor substrate of InP, as shown in FIG.
On the surface of compound semiconductor substrate 1 made of InP substrate
An insulating film 2 made of Al 2 O 3 is formed with a surface layer 3 made of a composite of oxides of various types of In, oxides of various types of P, and the like.

従つて上述せる従来のMIS型半導体装置の製法
の場合、目的とするMIS型半導体装置を所期の良
好な特性を有するものとして得ることが出来ない
懽れを有するという欠点を有していた。即ち上述
せる従来のMIS型半導体装置の製法によつてその
MIS型半導体装置を、P型のInPである化合物半
導体基板内にその表面(主面)側よりN型の半導
体領域でなるソース領域及びドレイン領域がそれ
等間にチヤンネル領域を形成すべく形成され、そ
のチヤンネル領域の表面上にAl2O3でなるゲート
絶縁膜を介してゲート電極と配してなるMIS型電
界効果トランジスタとして得、そしてこの場合の
ゲート絶縁膜を上述せる従来のMIS型半導体装置
の製法に含む化合物半導体基板の表面上に絶縁膜
を形成する工程によつて形成する場合で例示すれ
ば、その従来の製法によつて得られる上述せる
MIS型電界効果トランジスタが、特にそのソース
領域及びドレイン領域間に所要の電源を接続した
状態でソース領域及びゲート電極間に所要のバイ
アス電圧を与えてソース領域及びドレイン領域を
通るドレイン電流を流したときのそのドレイン電
流の時間に対する値でみて、その値が、第2図に
て曲線Aで示す如く、頭初はAl2O3でなるゲート
絶縁膜に於ける捕獲中心に電子が捕獲されるとい
う理由で時間と共に僅かに減少するも、ある時間
を過ぎた時点よりは、InPでなる化合物半導体基
板の表面上のAl2O3でなるゲート絶縁膜が第1図
にて上述せる如くにInの種々の形の酸化物、Pの
種々の形の酸化物等の複合体でなる表面層を介し
て形成されていてその表面層に於ける捕獲中心に
電子が捕獲されるという理由で時間と共急激に減
少するという、望ましくないドレイン電流特性の
得られる懽れを有するという欠点を有していた。
Therefore, the above-mentioned conventional method for manufacturing an MIS type semiconductor device has the disadvantage that it is not possible to obtain the desired MIS type semiconductor device with desired good characteristics. In other words, the conventional MIS type semiconductor device manufacturing method described above
A MIS type semiconductor device is constructed by forming a source region and a drain region made of an N-type semiconductor region from the front surface (principal surface) side in a compound semiconductor substrate made of P-type InP so as to form a channel region between them. A MIS type field effect transistor is obtained in which a gate electrode is arranged on the surface of the channel region via a gate insulating film made of Al 2 O 3 , and the gate insulating film in this case is the conventional MIS type semiconductor described above. For example, in the case where an insulating film is formed by a step of forming an insulating film on the surface of a compound semiconductor substrate included in the manufacturing method of a device, the above-mentioned film obtained by the conventional manufacturing method is
A MIS type field effect transistor has a drain current flowing through the source region and the drain region by applying a necessary bias voltage between the source region and the gate electrode with a necessary power supply connected between the source region and the drain region. Looking at the value of the drain current over time, as shown by curve A in Figure 2, electrons are initially captured at the capture center in the gate insulating film made of Al 2 O 3 . For this reason, it decreases slightly over time, but after a certain point, the gate insulating film made of Al 2 O 3 on the surface of the compound semiconductor substrate made of InP becomes In as described above in FIG. It is formed through a surface layer consisting of a composite of various forms of oxide of It has the disadvantage that it has the tendency to exhibit undesirable drain current characteristics in which the drain current characteristic suddenly decreases.

依つて本発明は上述せる欠点のない新規な化合
物半導体基板を用いたMIS型半導体装置の製法を
提案せんとするもので、以下詳述する所より明ら
かとなるであろう。
Therefore, the present invention proposes a method for manufacturing an MIS type semiconductor device using a novel compound semiconductor substrate free from the above-mentioned drawbacks, which will become clear from the detailed description below.

本発明は、冒頭にて前述せる従来のMIS型半導
体装置の製法の場合と同様に、化合物半導体基板
の表面上のに絶縁膜を形成する工程を含んで化合
物半導体基板を用いたMIS型半導体装置を得る
MIS型半導体装置の製法というのであるが、その
MIS型半導体装置の製法に於て含む化合物半導体
基板の表面上に絶縁膜を形成する工程が、以下述
べる如くい、冒頭にて前述せる従来のMIS型半導
体装置の製法に於ける工程とは異なることを除い
ては、冒頭にて前述せる従来のMIS型半導体装置
の製法と同様であるものである。
The present invention provides an MIS type semiconductor device using a compound semiconductor substrate including a step of forming an insulating film on the surface of the compound semiconductor substrate, as in the case of the conventional MIS type semiconductor device manufacturing method mentioned at the beginning. get
The manufacturing method for MIS type semiconductor devices is
The process of forming an insulating film on the surface of a compound semiconductor substrate, which is involved in the manufacturing method of MIS semiconductor devices, is different from the process of the conventional MIS semiconductor device manufacturing method mentioned at the beginning, as described below. Other than this, this method is the same as the conventional MIS type semiconductor device manufacturing method described at the beginning.

依つて以下主として本発明による化合物半導体
基板の表面上に絶縁膜を形成する工程につき述べ
るに、本発明による化合物半導体基板の表面上に
絶縁膜を形成する工程の実施例に於ては、アルゴ
ン等の不活性ガスの得られる不活性ガス源31、
アルミニウムトリイソプロポキサイドガス等の絶
縁膜形成用ガスの得られる絶縁膜形成用ガス源3
2、及び塩化水素ガスの得られる塩化水素ガス源
33に夫々開閉弁34,35,及び36を介して
連結せるガス供給管37、及び排気手段(図示せ
ず)に連結せるガス排出管38を外部に導出し、
且外部より端子片39及び40を介してヒータ4
1を有する基板支持台42を内装せる反応炉43
が用意され、その反応炉43内の基板支持台42
上に予め得られるInP,GaAs,GaInAsP等でな
る化合物半導体基板44が支持せしめられる。
Therefore, the process of forming an insulating film on the surface of a compound semiconductor substrate according to the present invention will be mainly described below. an inert gas source 31 from which an inert gas is obtained;
Insulating film forming gas source 3 from which insulating film forming gas such as aluminum triisopropoxide gas can be obtained
2, a gas supply pipe 37 connected to a hydrogen chloride gas source 33 from which hydrogen chloride gas is obtained via on-off valves 34, 35, and 36, and a gas exhaust pipe 38 connected to an exhaust means (not shown). Externally,
In addition, the heater 4 is connected from the outside via the terminal pieces 39 and 40.
Reaction furnace 43 in which a substrate support stand 42 having 1 is housed
is prepared, and the substrate support stand 42 in the reactor 43 is prepared.
A compound semiconductor substrate 44 made of InP, GaAs, GaInAsP, etc. obtained in advance is supported thereon.

而して先ず排気手段を作動せしめて反応炉43
内の気体をガス排出管38を介して外部に放出せ
しめ乍ら、反応炉43内に不活性ガス源31より
開閉弁34を介して不活性ガスを供給し、反応炉
43内の気体が酸濁素を含まざる不活性ガスに置
換された所で、反応管43内に塩化水素ガス源3
5より開閉弁36を介して塩化水素ガスを供給せ
しめ、一方ヒータ41への通電をなさしめて化合
物半導体基板44を基板支持台42を介して所要
の温度(化合物半導体基板44がInPでなる場合
200〜300℃の温度)に加熱し、斯くして塩化水素
ガスを用いた気相エツチングにより化合物半導体
基板44をその表面より所要瑠の厚さ例えば500
Å以上の厚さに亘つて除去してその化合物半導体
基板44にその材料による新たな表面を得る。
First, the exhaust means is activated to remove the reactor 43.
While releasing the gas inside the reactor 43 to the outside through the gas exhaust pipe 38, an inert gas is supplied into the reactor 43 from the inert gas source 31 through the on-off valve 34, so that the gas inside the reactor 43 becomes acidic. At the point where the gas is replaced with an inert gas that does not contain turbidity, a hydrogen chloride gas source 3 is introduced into the reaction tube 43.
5, hydrogen chloride gas is supplied via the on-off valve 36, while the heater 41 is energized and the compound semiconductor substrate 44 is heated via the substrate support 42 to the required temperature (when the compound semiconductor substrate 44 is made of InP).
The compound semiconductor substrate 44 is heated to a temperature of 200 to 300° C.) and then vapor phase etched using hydrogen chloride gas to remove the compound semiconductor substrate 44 from its surface to a required thickness of, for example, 500° C.
A new surface of the compound semiconductor substrate 44 made of the material is obtained by removing the material to a thickness of .ANG. or more.

次に塩化水素ガス源33よりの塩化水素ガスの
反応炉43内への供給を開閉弁36によつて停止
せしめ、反応炉43内の塩化水素ガスを不活性ガ
ス源31より供給されている不活性ガスによつて
ガス排気管38を通じて外部に放出し、反応炉4
3内が塩化水素ガスを含まざる不活性ガスの雰囲
気になつた所で、反応炉43内に絶縁膜形成用ガ
ス源32よりの絶縁膜形成用ガスを開閉弁35を
介して供給し、一方ヒータ41への通電により化
合物半導体基板44を所要の温度(化合物半導体
基板44がInPでなり、又絶縁膜形成用ガスがア
ルミニウムトリイソプロポキサイドガスである場
合300〜400℃の温度)に加熱し、斯くて絶縁膜形
成用ガスを用いたCVD法により化合物半導体基
板44のその材料による新たな表面上に絶縁膜を
形成する。
Next, the supply of hydrogen chloride gas from the hydrogen chloride gas source 33 into the reactor 43 is stopped by the on-off valve 36, and the hydrogen chloride gas in the reactor 43 is replaced with the inert gas supplied from the inert gas source 31. The active gas is discharged to the outside through the gas exhaust pipe 38 and the reactor 4
3 becomes an inert gas atmosphere that does not contain hydrogen chloride gas, the insulating film forming gas from the insulating film forming gas source 32 is supplied into the reactor 43 via the on-off valve 35, while By energizing the heater 41, the compound semiconductor substrate 44 is heated to a required temperature (300 to 400° C. when the compound semiconductor substrate 44 is made of InP and the insulating film forming gas is aluminum triisopropoxide gas). Then, an insulating film is formed on the new surface of the compound semiconductor substrate 44 made of that material by CVD using an insulating film forming gas.

以上にて本発明によるMIS型半導体装置の製法
の実施例が明らかとなつたが、斯る製法によれ
ば、それが含む化合物半導体基板の表面上に絶縁
膜を形成する工程が、化合物半導体基板44を反
応炉43内に配した状態で、反応炉43内に塩化
水素ガスを供給してその塩化水素ガスを用いた気
相エツチングにより化合物半導体基板44にその
材料による新たな表面を得、次で反応炉43内に
絶縁膜用ガスを供給してその絶縁膜形成用ガスを
用いたCVD法により化合物半導体基板44のそ
の材料による新たな表面上に絶縁膜を形成すると
いう工程であり、而してその工程に於て化合物半
導体基板に得られるその材料による新たな表面が
空気に触れる懽れは全くなく、従つて化合物半導
体基板44の表面上の絶縁膜が、冒頭にて前述せ
る従来の製法の場合の如くに、化合物半導体基板
の材料の種々の形の酸化物の複合体でなる表面層
を介して形成される懽れがなく、、化合物半導体
基板44の材料の表面上に直接形成されるもので
ある。即ち、今化合物半導体基板44が冒頭にて
前述せる従来の場合と同様にInPでなるものと
し、又そのInPでなる化合物半導体基板の新たな
表面上にAl2O3でなる絶縁膜を形成する場合で例
示すれば、第4図に示す如くInPでなる化合物半
導体基板44の表面上のAl2O3でなる絶縁膜45
が、そのnPである化合物半導体基板44の材料
による表面上に直接形成されるものである。
As described above, an embodiment of the method for manufacturing an MIS type semiconductor device according to the present invention has been clarified. 44 is placed in the reactor 43, hydrogen chloride gas is supplied into the reactor 43, and gas phase etching is performed using the hydrogen chloride gas to obtain a new surface of the material on the compound semiconductor substrate 44. In this process, an insulating film gas is supplied into the reactor 43 and an insulating film is formed on the new surface of the compound semiconductor substrate 44 using the same material by CVD using the insulating film forming gas. In this process, there is no possibility that the new surface of the material obtained on the compound semiconductor substrate comes into contact with air, and therefore, the insulating film on the surface of the compound semiconductor substrate 44 is different from that of the conventional material mentioned at the beginning. Unlike the manufacturing method, there is no layer formed through a surface layer made of a composite of various forms of oxides of the material of the compound semiconductor substrate, and it is formed directly on the surface of the material of the compound semiconductor substrate 44. It is something that will be done. That is, the compound semiconductor substrate 44 is now made of InP as in the conventional case described at the beginning, and an insulating film made of Al 2 O 3 is formed on the new surface of the compound semiconductor substrate made of InP. For example, as shown in FIG. 4, an insulating film 45 made of Al 2 O 3 on the surface of a compound semiconductor substrate 44 made of InP.
is formed directly on the surface of the nP material of the compound semiconductor substrate 44.

従つて本発明によりMIS型半導体装置の製法に
よれば、冒頭にて前述せる従来の製法の場合の如
くに、目的とせるMIS型半導体装置を所期の良好
な特性を有するものとして得ることが出来ない懽
れを有するということがなく、目的とせるMIS型
半導体装置を所期の良好な特性を有するものとし
て得ることが出来るという大なる特徴を有するも
のである。因みに上述せる本発明のMIS型半導体
装置の製法によつてそのMIS型半導体装置を、従
来のMIS型半導体装置の製法につき前述せると同
様に、P型のInPでなる化合物半導体基板内にそ
の表面(主面)側よりN型の半導体領域でなるソ
ース領域及びドレイン領域がそれ等間にチヤンネ
ル領域を形成すべく形成され、そのチヤンネル領
域の表面上にAl2O3でなるゲート絶縁膜を介して
ゲート電極を配してなるMIS型電界効果トランジ
スタとして得、然し乍らその場合のゲート絶縁膜
を上述せる本発明のMIS型半導体装置の製法に含
む化合物半導体基板の表面上に絶縁膜を形成する
工程によつて形成する場合で例示すれば、その本
発明の製法によつて得られる上述せるMIS型電界
効果トランジスタが、そのソース領域及びドレイ
ン領域間に所要の電源を接続した状態でソース領
域及びゲート電極間に所要のバイアス電圧を与え
てソース領域及びドレイン領域を通るドレイン電
流を流したときの、そのドレイン電流の時間に対
する値でみて、その値が時間の長い経過にも拘ら
ず、第5図にて線B突で示す如く、Al2O3でなる
るゲート絶縁膜に於ける捕獲中心に電子が捕獲さ
れるという理由により時間と共に僅かに減少する
丈けであるという前述せる従来の製法によつて得
られたMIS型電界効果トランジスタの第5図にて
曲線A(第2図の曲線Aと同じ)に示されている
ドレイン電流特性より、大きく改善せるドレイン
電流特性が得られるものである。
Therefore, according to the method for manufacturing an MIS type semiconductor device according to the present invention, it is possible to obtain a target MIS type semiconductor device having desired good characteristics, as in the case of the conventional manufacturing method mentioned at the beginning. It has the great feature that it does not have an undesirable appearance, and that it is possible to obtain the desired MIS type semiconductor device with the desired good characteristics. Incidentally, by the above-mentioned method for manufacturing an MIS-type semiconductor device of the present invention, the surface of the MIS-type semiconductor device can be fabricated within a compound semiconductor substrate made of P-type InP, in the same manner as described above for the conventional method for manufacturing an MIS-type semiconductor device. A source region and a drain region made of N-type semiconductor regions are formed from the (principal surface) side to form a channel region between them, and a gate insulating film made of Al 2 O 3 is formed on the surface of the channel region. A step of forming an insulating film on the surface of a compound semiconductor substrate included in the above-mentioned method for manufacturing a MIS-type semiconductor device of the present invention is obtained as an MIS-type field effect transistor having a gate electrode arranged therein. For example, in the case where the MIS type field effect transistor described above obtained by the manufacturing method of the present invention is formed by the source region and the gate with the required power supply connected between the source region and the drain region, When a required bias voltage is applied between the electrodes and a drain current is caused to flow through the source region and drain region, the value of the drain current with respect to time shows that even though a long time has elapsed, the value is As shown by line B in Figure 1, the length decreases slightly over time due to the fact that electrons are captured at the capture center in the gate insulating film made of Al 2 O 3 . The drain current characteristics of the MIS field effect transistor thus obtained can be significantly improved over the drain current characteristics shown by curve A in FIG. 5 (same as curve A in FIG. 2). .

尚上述に施ては、MIS型半導体装置をMIS型電
界効果トランジスタとして得る場合の実施例を伴
つて本発明によるMIS型半導体装置の製法を説明
したが、本発明はこれを化合物半導体基板及び絶
縁膜間の界面特性を利用せる種々合の突MIS型半
導体装置を得る場合に適用し得、又その場合の化
合物半導体基板がInPである場合ばかりでなく
GaAs,GaInAsP等である場合であつても、更に
化合物半導体基板の表面上の絶縁膜をAl2O3でな
るものとして形成する場合ばかりでなくSiO2
Si3N4等でなるものとして形成する場合にも本発
明を適用し得ること明らかであろう。
In the above, the method for manufacturing an MIS type semiconductor device according to the present invention has been explained with reference to an embodiment in which the MIS type semiconductor device is obtained as a MIS type field effect transistor. It can be applied to various types of MIS type semiconductor devices that utilize the interfacial characteristics between films, and is not limited to cases where the compound semiconductor substrate is InP.
Even if GaAs, GaInAsP, etc. are used, the insulating film on the surface of the compound semiconductor substrate is not only formed of Al 2 O 3 but also SiO 2 , GaInAsP, etc.
It will be obvious that the present invention can also be applied to the case where it is formed of Si 3 N 4 or the like.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の化合物半導体基板を用いたMIS
型半導体装置の製法が含む工程によつて得られる
化合物半導体基板の表面上おの絶縁膜を示す略線
的断面図、第2図は従来の化合物半導体基板を用
いたMIS型半導体装置の製法によつて得られる
MIS型電界効果トランジスタのドレイン電流特性
を示す図、第3図は本発明による化合物半導体基
板を用いたMIS型半導体装置の製法に用いられる
反応炉を示す略線図、第4図は本発明による化合
物半導体基板を用いたMIS型半導体装置の製法が
含む工程によつて得られる化合物半導体基板の表
面上の絶縁膜を示す略線的断面図、第5図は本発
明による化合物半導体基板を用いたMIS型半導体
装置の製法によつて得られるMIS型電界効果トラ
ンジスタのドレイン電流特性を示す図である。 図中、1は化合物半導体基板、2は絶縁膜、3
は表面層、31は不活性ガス源、32は絶縁膜形
成用ガス源、33は塩化水素ガス源、34〜36
は開閉弁、37はガス供給管、38はガス排出
管、41はヒータ、42は基板支持台、43は反
応炉、44は化合物半導体基板、45は絶縁膜を
夫々示す。
Figure 1 shows MIS using a conventional compound semiconductor substrate.
Figure 2 is a schematic cross-sectional view showing an insulating film on the surface of a compound semiconductor substrate obtained by the process included in the manufacturing method of a MIS type semiconductor device using a conventional compound semiconductor substrate. obtained by twisting
A diagram showing the drain current characteristics of an MIS type field effect transistor, FIG. 3 is a schematic diagram showing a reaction furnace used in the method for manufacturing an MIS type semiconductor device using a compound semiconductor substrate according to the present invention, and FIG. 4 is a diagram according to the present invention. FIG. 5 is a schematic cross-sectional view showing an insulating film on the surface of a compound semiconductor substrate obtained by the process included in the manufacturing method of an MIS type semiconductor device using a compound semiconductor substrate, and FIG. FIG. 3 is a diagram showing drain current characteristics of an MIS field effect transistor obtained by a method for manufacturing an MIS semiconductor device. In the figure, 1 is a compound semiconductor substrate, 2 is an insulating film, and 3 is a compound semiconductor substrate.
31 is a surface layer, 31 is an inert gas source, 32 is an insulating film forming gas source, 33 is a hydrogen chloride gas source, 34 to 36
37 is a gas supply pipe, 38 is a gas discharge pipe, 41 is a heater, 42 is a substrate support stand, 43 is a reactor, 44 is a compound semiconductor substrate, and 45 is an insulating film.

Claims (1)

【特許請求の範囲】[Claims] 1 化合物半導体基板を反応炉内に配した状態
で、該反応炉内に塩化水素ガスを供給して当該塩
化水素ガスを用いた気相エツチングにより上記化
合物半導体基板にその材料による新たな表面を
得、次で上記反応炉内に絶縁膜形成用ガスを供給
して当該絶縁膜形成用ガスを用いたCVD法によ
り上記化合物半導体基板のその材料による新たな
表面上に絶縁膜を形成する工程を含む事を特徴と
する化合物半導体基板を用いたMIS型半導体装置
の製法。
1. With the compound semiconductor substrate placed in a reactor, hydrogen chloride gas is supplied into the reactor, and gas phase etching is performed using the hydrogen chloride gas to obtain a new surface of the material on the compound semiconductor substrate. , and then supplying an insulating film forming gas into the reactor and forming an insulating film on a new surface of the compound semiconductor substrate made of the material by a CVD method using the insulating film forming gas. A method for manufacturing an MIS type semiconductor device using a compound semiconductor substrate, which is characterized by:
JP6024880A 1980-05-06 1980-05-06 Manufacture of mis type semiconductor device Granted JPS56157063A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6024880A JPS56157063A (en) 1980-05-06 1980-05-06 Manufacture of mis type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6024880A JPS56157063A (en) 1980-05-06 1980-05-06 Manufacture of mis type semiconductor device

Publications (2)

Publication Number Publication Date
JPS56157063A JPS56157063A (en) 1981-12-04
JPS6161547B2 true JPS6161547B2 (en) 1986-12-26

Family

ID=13136679

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6024880A Granted JPS56157063A (en) 1980-05-06 1980-05-06 Manufacture of mis type semiconductor device

Country Status (1)

Country Link
JP (1) JPS56157063A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010067525A1 (en) * 2008-12-08 2010-06-17 住友化学株式会社 Semiconductor device, process for producing semiconductor device, semiconductor substrate, and process for producing semiconductor substrate

Also Published As

Publication number Publication date
JPS56157063A (en) 1981-12-04

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