JPH05259154A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH05259154A JPH05259154A JP4650892A JP4650892A JPH05259154A JP H05259154 A JPH05259154 A JP H05259154A JP 4650892 A JP4650892 A JP 4650892A JP 4650892 A JP4650892 A JP 4650892A JP H05259154 A JPH05259154 A JP H05259154A
- Authority
- JP
- Japan
- Prior art keywords
- film
- oxide film
- silicon oxide
- polycrystalline silicon
- silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Electrodes Of Semiconductors (AREA)
- Formation Of Insulating Films (AREA)
- Non-Volatile Memory (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は半導体装置の製造方法に
関し、特に多結晶シリコン膜上に設ける酸化シリコン膜
の形成方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a silicon oxide film provided on a polycrystalline silicon film.
【0002】[0002]
【従来の技術】半導体基板上に設けた多結晶シリコン膜
上に酸化シリコン膜を成膜して半導体素子の一部を構成
する方法が広く用いられている。2. Description of the Related Art A method of forming a silicon oxide film on a polycrystalline silicon film provided on a semiconductor substrate to form a part of a semiconductor device is widely used.
【0003】図3(a)〜(d)は従来の半導体装置の
製造方法を説明するための工程順に示した半導体チップ
の断面図である。FIGS. 3A to 3D are cross-sectional views of a semiconductor chip shown in the order of steps for explaining a conventional method for manufacturing a semiconductor device.
【0004】先ず、図3(a)に示すように、シリコン
基板1の表面に選択的に設けて素子形成領域を区画する
素子間分離用のフィールド酸化膜2及び素子形成領域の
表面に設けたゲート酸化膜3を含む表面に化学的気相成
長(以下CVDと記す)法によって第1の多結晶シリコ
ン膜4を堆積して電気抵抗を下げる為に不純物を拡散
し、フォトリソグラフィ技術及び蝕刻技術によりパター
ニングする。First, as shown in FIG. 3 (a), a field oxide film 2 for element isolation for selectively providing an element formation region on the surface of a silicon substrate 1 and an element formation area is provided. A first polycrystalline silicon film 4 is deposited on the surface including the gate oxide film 3 by a chemical vapor deposition (hereinafter referred to as CVD) method, impurities are diffused in order to reduce electric resistance, and photolithography technology and etching technology are used. Patterning by.
【0005】次に、図3(b)に示すように、酸素雰囲
気中での加熱により、多結晶シリコン膜4の表面に熱酸
化膜5を形成する。Next, as shown in FIG. 3B, a thermal oxide film 5 is formed on the surface of the polycrystalline silicon film 4 by heating in an oxygen atmosphere.
【0006】次に、図3(c)に示すように、熱酸化膜
5を含む表面にCVD法により第2の多結晶シリコン膜
7を堆積し電気抵抗を下げる為に不純物を拡散する。Next, as shown in FIG. 3C, a second polycrystalline silicon film 7 is deposited on the surface including the thermal oxide film 5 by the CVD method and impurities are diffused in order to reduce the electric resistance.
【0007】次に、図3(d)に示すように、フォトリ
ソグラフィ技術及び蝕刻技術により多結晶シリコン膜7
と熱酸化膜5と多結晶シリコン膜4を選択的に順次エッ
チングしてEPROM素子のフローティングゲート電極
及びコントロールゲート電極を形成する。Next, as shown in FIG. 3D, the polycrystalline silicon film 7 is formed by the photolithography technique and the etching technique.
Then, the thermal oxide film 5 and the polycrystalline silicon film 4 are selectively and sequentially etched to form a floating gate electrode and a control gate electrode of the EPROM element.
【0008】なお、多結晶シリコン膜7と熱酸化膜5と
多結晶シリコン膜4の蝕刻は、3ステップの異方性ドラ
イエッチングによって行なわれ、第1ステップと第3ス
テップはシリコン膜のエッチングに対して酸化シリコン
膜のエッチング選択比の大なる条件で、第2ステップ
は、酸化シリコン膜のエッチングに対してシリコン膜の
エッチング選択比の大なる条件で行なわれる。The polycrystal silicon film 7, the thermal oxide film 5 and the polycrystal silicon film 4 are etched by anisotropic dry etching in three steps. The first step and the third step are etching of the silicon film. On the other hand, the second step is performed under the condition that the etching selection ratio of the silicon oxide film is large, and the etching selection ratio of the silicon film is large with respect to the etching of the silicon oxide film.
【0009】[0009]
【発明が解決しようとする課題】この従来の半導体装置
の製造方法は、第1の多結晶シリコン膜の表面を、熱酸
化する際に熱酸化レートが多結晶シリコン膜の各結晶粒
の面方位および粒界で異なるため、成膜された熱酸化膜
の膜厚分布に局所的不均一性を生じ、静電耐圧に対する
ウィークポイントを有するという問題点があった。In this conventional method for manufacturing a semiconductor device, the surface orientation of each crystal grain of the polycrystalline silicon film has a thermal oxidation rate when the surface of the first polycrystalline silicon film is thermally oxidized. Since the grain boundaries are different from each other, there is a problem that the formed thermal oxide film has a local non-uniformity in the film thickness distribution and has a weak point with respect to the electrostatic breakdown voltage.
【0010】又、不純物を拡散した多結晶シリコン膜の
表面を熱酸化する為、成膜された熱酸化膜が多くの不純
物を含んでしまい、酸化膜の信頼性を低下させるという
問題点があった。Further, since the surface of the polycrystalline silicon film in which the impurities are diffused is thermally oxidized, the formed thermal oxide film contains a large amount of impurities, which causes a problem that the reliability of the oxide film is lowered. It was
【0011】このような膜厚分布の局所的不均一性は、
多結晶シリコン膜上の熱酸化膜を誘電体とする静電容量
素子の信頼性を低下させる要因となっている。Such local non-uniformity of the film thickness distribution is
This is a factor that lowers the reliability of the capacitance element having the thermal oxide film on the polycrystalline silicon film as a dielectric.
【0012】[0012]
【課題を解決するための手段】本発明の半導体装置の製
造方法は、半導体基板上に多結晶シリコン膜を形成する
工程と、前記多結晶シリコン膜の表面に液相成長法によ
り酸化シリコン膜を形成する工程と、前記酸化シリコン
膜を不活性ガス雰囲気中でアニールする工程とを含んで
構成される。A method of manufacturing a semiconductor device according to the present invention comprises a step of forming a polycrystalline silicon film on a semiconductor substrate, and a silicon oxide film formed on the surface of the polycrystalline silicon film by liquid phase epitaxy. It comprises a step of forming and a step of annealing the silicon oxide film in an inert gas atmosphere.
【0013】[0013]
【実施例】次に、本発明について図面を参照して説明す
る。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.
【0014】図1(a)〜(d)は本発明の第1の実施
例の製造方法を説明するための工程順に示した半導体チ
ップの断面図である。FIGS. 1A to 1D are cross-sectional views of a semiconductor chip showing the order of steps for explaining the manufacturing method of the first embodiment of the present invention.
【0015】先ず、図1(a)に示すように、シリコン
基板1の表面を選択的に熱酸化して素子間分離用フィー
ルド酸化膜2を形成し、フィールド酸化膜2により区画
された素子形成領域の表面を熱酸化してゲート酸化膜3
を形成する。次に、ゲート酸化膜3を含む表面にCVD
法により第1の多結晶シリコン膜4を堆積して電気抵抗
を下げる為に不純物を拡散した後フォトリソグラフィ技
術及び蝕刻技術によりパターニングする。First, as shown in FIG. 1 (a), the surface of a silicon substrate 1 is selectively thermally oxidized to form a field oxide film 2 for element isolation, and an element formed by the field oxide film 2 is formed. Gate oxide film 3 by thermally oxidizing the surface of the region
To form. Next, CVD is performed on the surface including the gate oxide film 3.
The first polycrystalline silicon film 4 is deposited by the method and impurities are diffused in order to reduce the electric resistance, and then patterned by the photolithography technique and the etching technique.
【0016】次に、図1(b)に示すように、多結晶シ
リコン膜4を含む表面に液相成長法により酸化シリコン
膜6を成膜し、不活性ガス雰囲気で900℃以上のアニ
ールを行なう。Next, as shown in FIG. 1B, a silicon oxide film 6 is formed on the surface including the polycrystalline silicon film 4 by a liquid phase growth method, and annealed at 900 ° C. or higher in an inert gas atmosphere. To do.
【0017】次に、図1(c)に示すように、酸化シリ
コン膜6の上にCVD法により第2の多結晶シリコン膜
7を堆積して電気抵抗を下げる為に不純物を拡散する。Next, as shown in FIG. 1C, a second polycrystalline silicon film 7 is deposited on the silicon oxide film 6 by the CVD method and impurities are diffused in order to reduce the electric resistance.
【0018】次に、図1(d)に示すように、フォトリ
ソグラフィ技術及び蝕刻技術により多結晶シリコン膜7
と酸化シリコン膜6と多結晶シリコン膜4を選択的に順
次エッチングしてEPROM素子のフローティングゲー
ト電極及びコントロールゲート電極を形成する。なお、
多結晶シリコン膜7と酸化シリコン膜6と多結晶シリコ
ン膜4の蝕刻は、従来例と同様の3ステップの異方性ド
ライエッチングによって行なわれる。Next, as shown in FIG. 1D, the polycrystalline silicon film 7 is formed by the photolithography technique and the etching technique.
Then, the silicon oxide film 6 and the polycrystalline silicon film 4 are selectively and sequentially etched to form a floating gate electrode and a control gate electrode of the EPROM element. In addition,
Etching of the polycrystalline silicon film 7, the silicon oxide film 6, and the polycrystalline silicon film 4 is performed by three-step anisotropic dry etching similar to the conventional example.
【0019】又酸化シリコン膜6の成長は、ケイ弗化水
素酸(H2 SiF6 )水溶液が、Further, the growth of the silicon oxide film 6 is performed by using a hydrosilicofluoric acid (H 2 SiF 6 ) solution.
【0020】 [0020]
【0021】の平衡状態を維持し、SiO2 の飽和状態
を形成している所へ、ホウ酸(H3 BO3 )を添加する
事により、By maintaining the equilibrium state of and adding boric acid (H 3 BO 3 ) to the place where a saturated state of SiO 2 is formed,
【0022】 [0022]
【0023】の反応によりHFが消費され、SiO2 の
過飽和状態が実現し、SiO2 が析出する事で行なわれ
る。The reaction HF is consumed by the supersaturation state of SiO 2 is achieved, it takes place in that the SiO 2 is precipitated.
【0024】液相成長が成立する条件としては、約33
%のH2 SiF6 水溶液の場合で、水溶液中のH3 BO
3 濃度の50×10-3mol/l以上にする事で成長が
始まる。The conditions for establishing liquid phase growth are about 33
% H 2 SiF 6 aqueous solution, H 3 BO in the aqueous solution
3 Concentration Growth at 50 × 10 -3 mol / l can be more starts.
【0025】一例を挙げると、液温23℃でH3 BO3
濃度を100×10-3mol/lにすると、約0.1n
m/minの酸化シリコン膜の成長レートが得られる。
この時の膜厚均一性は4インチ径ウェーハで±2%,ア
ニール時の膜収縮率は900℃アニールで3.3%と膜
厚均一性が良くかつ膜収縮率の小さい膜が得られる。加
えて成膜された酸化シリコン膜はノンドープの膜であ
り、不純物の拡散は、アニール時の熱拡散のみの為、ラ
ンプアニール等短時間の高温アニールを採用する事で、
不純物の含有の少ない酸化シリコン膜が形成できる。As an example, H 3 BO 3 is used at a liquid temperature of 23 ° C.
When the concentration is 100 × 10 -3 mol / l, it is about 0.1n.
A silicon oxide film growth rate of m / min is obtained.
At this time, the film thickness uniformity is ± 2% for a 4-inch diameter wafer, and the film shrinkage ratio during annealing is 900% at 900 ° C. Annealing, and a film having good film thickness uniformity and a small film shrinkage ratio can be obtained. In addition, the silicon oxide film formed is a non-doped film, and the diffusion of impurities is only thermal diffusion during annealing. Therefore, by adopting short-time high-temperature annealing such as lamp annealing,
A silicon oxide film containing less impurities can be formed.
【0026】図2(a)〜(d)は本発明の第2の実施
例の製造方法を説明するための工程順に示した半導体チ
ップの断面図である。2 (a) to 2 (d) are sectional views of the semiconductor chip in the order of steps for explaining the manufacturing method of the second embodiment of the present invention.
【0027】先ず、図2(a)に示すように、シリコン
基板1の上に設けた素子分離用のフィールド酸化膜2の
上にCVD法によって第1の多結晶シリコン膜4を堆積
し、電気抵抗を下げる為に不純物を拡散する。First, as shown in FIG. 2A, a first polycrystalline silicon film 4 is deposited on a field oxide film 2 for element isolation provided on a silicon substrate 1 by a CVD method, and an electric field is formed. Impurities are diffused to reduce resistance.
【0028】次に、図2(b)に示すように、多結晶シ
リコン膜4の上に液相成長により酸化シリコン膜6を成
膜し、温度900℃の不活性ガス雰囲気でアニールした
後、酸化シリコン膜6の上にCVD法で窒化シリコン膜
8を成膜し、その表面を熱酸化して熱酸化膜9を成膜し
て酸化シリコン膜/窒化シリコン膜/酸化シリコン膜の
3層構造(以下ONO構造と記す)を形成する。Next, as shown in FIG. 2B, a silicon oxide film 6 is formed on the polycrystalline silicon film 4 by liquid phase growth and annealed in an inert gas atmosphere at a temperature of 900 ° C. A silicon nitride film 8 is formed on the silicon oxide film 6 by a CVD method, and the surface thereof is thermally oxidized to form a thermal oxide film 9 to form a three-layer structure of silicon oxide film / silicon nitride film / silicon oxide film. (Hereinafter referred to as ONO structure).
【0029】次に、図2(c)に示すように、熱酸化膜
9の上にCVD法によって第2の多結晶シリコン膜7を
堆積し、電気抵抗を下げる為に不純物を拡散する。Next, as shown in FIG. 2C, a second polycrystalline silicon film 7 is deposited on the thermal oxide film 9 by the CVD method, and impurities are diffused in order to reduce the electric resistance.
【0030】次に、図2(d)に示すように、フォトリ
ソグラフィ技術及び蝕刻技術により多結晶シリコン膜7
と、ONO構造及び多結晶シリコン膜4を選択的に順次
異方性ドライエッチングし、容量素子を形成する。Next, as shown in FIG. 2D, the polycrystalline silicon film 7 is formed by the photolithography technique and the etching technique.
Then, the ONO structure and the polycrystalline silicon film 4 are selectively subjected to anisotropic dry etching in order to form a capacitive element.
【0031】ここで、半導体基板上に成膜された多結晶
シリコン膜上に誘電体膜としてONO構造を形成する場
合、中間層の窒化シリコン膜の膜質もさることながら、
窒化シリコン膜の成膜に先立って成膜される厚さ数nm
の酸化シリコン膜の膜質も信頼性上重要な要素となる
が、これに液相成長法で形成した酸化シリコン膜を用い
る事で、下地のシリコン膜の膜質に影響されることな
く、高品質の酸化シリコン膜を成膜可能となる。Here, when an ONO structure is formed as a dielectric film on a polycrystalline silicon film formed on a semiconductor substrate, not only the quality of the intermediate silicon nitride film,
Thickness of several nm formed prior to the formation of the silicon nitride film
The quality of the silicon oxide film is also an important factor in terms of reliability, but by using a silicon oxide film formed by liquid phase epitaxy on this, high quality without being affected by the quality of the underlying silicon film. A silicon oxide film can be formed.
【0032】[0032]
【発明の効果】以上説明したように本発明は、半導体基
板上に形成された多結晶シリコン膜上に形成する酸化シ
リコン膜を、液相成長法を用いて成膜することにより、
膜厚均一性が良く、不純物の少ない酸化シリコン膜を高
精度に形成できるという効果を有する。As described above, according to the present invention, a silicon oxide film formed on a polycrystalline silicon film formed on a semiconductor substrate is formed by a liquid phase epitaxy method.
It has an effect that a film thickness uniformity is good and a silicon oxide film with few impurities can be formed with high precision.
【図1】本発明の第1の実施例を説明するための工程順
に示した断面図。1A to 1C are sectional views showing a process sequence for explaining a first embodiment of the present invention.
【図2】本発明の第2の実施例を説明するための工程順
に示した断面図。2A to 2D are sectional views showing a process sequence for explaining a second embodiment of the present invention.
【図3】従来の半導体装置の製造方法を説明するための
工程順に示した断面図。3A to 3C are cross-sectional views showing the order of steps for explaining a conventional method for manufacturing a semiconductor device.
1 シリコン基板 2 フィールド酸化膜 3 ゲート酸化膜 4,7 多結晶シリコン膜 5,9 熱酸化膜 6 酸化シリコン膜 8 窒化シリコン膜 1 Silicon substrate 2 Field oxide film 3 Gate oxide film 4,7 Polycrystalline silicon film 5,9 Thermal oxide film 6 Silicon oxide film 8 Silicon nitride film
Claims (2)
する工程と、前記多結晶シリコン膜の表面に液相成長法
により酸化シリコン膜を形成する工程と、前記酸化シリ
コン膜を不活性ガス雰囲気中でアニールする工程とを含
む事を特徴とする半導体装置の製造方法。1. A step of forming a polycrystalline silicon film on a semiconductor substrate, a step of forming a silicon oxide film on a surface of the polycrystalline silicon film by a liquid phase growth method, and a step of forming the silicon oxide film in an inert gas atmosphere. And a step of annealing in the semiconductor device.
F6 )水溶液にホウ酸(H3 BO3 )を添加して水溶液
中に生じる酸化シリコン(SiO2 )の過飽和状態から
酸化シリコン膜を析出する方法を含む請求項1記載の半
導体装置の製造方法。2. The liquid phase epitaxy method is hydrofluoric acid (H 2 Si).
2. The method for manufacturing a semiconductor device according to claim 1, further comprising a method of adding boric acid (H 3 BO 3 ) to an F 6 ) aqueous solution to deposit a silicon oxide film from a supersaturated state of silicon oxide (SiO 2 ) generated in the aqueous solution. ..
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4650892A JPH05259154A (en) | 1992-03-04 | 1992-03-04 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4650892A JPH05259154A (en) | 1992-03-04 | 1992-03-04 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH05259154A true JPH05259154A (en) | 1993-10-08 |
Family
ID=12749202
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4650892A Pending JPH05259154A (en) | 1992-03-04 | 1992-03-04 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH05259154A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07169735A (en) * | 1993-12-13 | 1995-07-04 | Nec Corp | Manufacture of semiconductor device |
US6514801B1 (en) | 1999-03-30 | 2003-02-04 | Seiko Epson Corporation | Method for manufacturing thin-film transistor |
US6593591B2 (en) | 1996-05-15 | 2003-07-15 | Seiko Epson Corporation | Thin film device provided with coating film, liquid crystal panel and electronic device, and method the thin film device |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6112034A (en) * | 1984-06-27 | 1986-01-20 | Nippon Sheet Glass Co Ltd | Formation of silicon oxide film on silicon substrate surface |
JPH0322551A (en) * | 1989-06-20 | 1991-01-30 | Nec Corp | Manufacture of semiconductor device |
-
1992
- 1992-03-04 JP JP4650892A patent/JPH05259154A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6112034A (en) * | 1984-06-27 | 1986-01-20 | Nippon Sheet Glass Co Ltd | Formation of silicon oxide film on silicon substrate surface |
JPH0322551A (en) * | 1989-06-20 | 1991-01-30 | Nec Corp | Manufacture of semiconductor device |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07169735A (en) * | 1993-12-13 | 1995-07-04 | Nec Corp | Manufacture of semiconductor device |
US6593591B2 (en) | 1996-05-15 | 2003-07-15 | Seiko Epson Corporation | Thin film device provided with coating film, liquid crystal panel and electronic device, and method the thin film device |
US6514801B1 (en) | 1999-03-30 | 2003-02-04 | Seiko Epson Corporation | Method for manufacturing thin-film transistor |
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