JPS6159786A - Production of chip hall element - Google Patents

Production of chip hall element

Info

Publication number
JPS6159786A
JPS6159786A JP59181502A JP18150284A JPS6159786A JP S6159786 A JPS6159786 A JP S6159786A JP 59181502 A JP59181502 A JP 59181502A JP 18150284 A JP18150284 A JP 18150284A JP S6159786 A JPS6159786 A JP S6159786A
Authority
JP
Japan
Prior art keywords
film
vapor deposition
electrode
sensitive element
electrode film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59181502A
Other languages
Japanese (ja)
Inventor
Masanori Konuma
小沼 正憲
Reizou Sunaga
砂永 礼三
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Pioneer Corp
Original Assignee
Pioneer Electronic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Pioneer Electronic Corp filed Critical Pioneer Electronic Corp
Priority to JP59181502A priority Critical patent/JPS6159786A/en
Publication of JPS6159786A publication Critical patent/JPS6159786A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N52/00Hall-effect devices
    • H10N52/01Manufacture or treatment

Abstract

PURPOSE:To obtain an overlapped portion between an electrode film and a magnetic sensitive element film and to form the electrode film over the side face of a dividing groove, by changing the incidence angle of vapor deposition made between the surface of master plate and the upstream direction of metallic vapor flow in the process of vapor deposition for forming the electrode film. CONSTITUTION:Grooves 8 are half cut in a master plate 5 so as to divide it into a plurality of substrates in lattice form. A magnetic sensitive element film of InSb is formed on the main surface of the master plate 5, and then a first electrode 3a is vapor deposited thereon. A second electrode film 3b is then vapor deposited so as to cover from the surface of the substrate 1 to the side face of the groove 8. A first protective film of Al2O3 is provided for protecting the joining area between the magnetic sensitive element film and the electrode films, and the magnetic sensitive element film. A second protective film of resin is deposited on the first protective film. Thus, provided is a two- layer protective film 4 consisting of the lower alumina layer and of the upper resin layer covering the joining area between the magnetic sensitive element film and the electrode films and the magnetic sensitive element film. After that, the substrate is scribed and solder is dipped on the electrode films.

Description

【発明の詳細な説明】 11丸1 本発明は、チップホール素子の製造方法に関する。[Detailed description of the invention] 11 circles 1 The present invention relates to a method for manufacturing a chip Hall element.

1旦且■− チップホール素子は従来形のホール素子をより小型、a
感度化するために開発されたものである。
1 and ■ - The chip Hall element is a smaller and smaller version of the conventional Hall element.
It was developed to increase sensitivity.

かかるチップホール素子は日本国特許願第59−100
132Mの明1II1日にその製造方法がUn示されて
いる。このチップホール素子は第1図(a)及び(b)
にその平面及び断面を示すように基板1上に感磁素子膜
2、電極113及び保護膜4を真空蒸着法で積層したも
のである。かかるチップホ−ル素子の製造方法の工程に
おいては、基板1を区画する溝を施した原板5を用意し
て、第2図−(a)に示すように基板1各々にマスキン
グをして感磁素子膜2を蒸着し、第2図(b)に示すよ
うにその上にマスキングをして電極F13を基板1の主
面から側面にまで亘って蒸着積層し、第2図(C)に示
すように感磁素子膜2と電極膜3との接続部分(重なる
部分)及び感磁素子膜2を保護するように保護膜4がマ
スキングをして蒸着される。
Such a chip Hall element is disclosed in Japanese Patent Application No. 59-100.
132M, on the 1st day of the 1st century, the method of its manufacture is shown in Un. This chip Hall element is shown in Fig. 1 (a) and (b).
As shown in its plane and cross section, a magnetically sensitive element film 2, an electrode 113, and a protective film 4 are laminated on a substrate 1 by vacuum evaporation. In the steps of the manufacturing method for such a chip hole element, an original plate 5 with grooves dividing the substrate 1 is prepared, and each substrate 1 is masked and magnetically sensitive as shown in FIG. 2-(a). An element film 2 is deposited, masked thereon as shown in FIG. 2(b), and an electrode F13 is deposited and laminated from the main surface to the side surfaces of the substrate 1, as shown in FIG. 2(C). A protective film 4 is masked and deposited so as to protect the connecting portion (overlapping portion) between the magnetically sensitive element film 2 and the electrode film 3 and the magnetically sensitive element film 2.

その後、基板毎に原板を切断してチップホールとなる素
子チップを得ているのである。
Thereafter, the original plate is cut for each substrate to obtain element chips that serve as chip holes.

上記した先行例の製造方法においては第3図(a)に示
す如(電極膜M着工程において蒸着用メタルマスク6を
基板上の所定の位置に置き感磁素子膜2と電極flli
!3とが重なる部分も含めて基板全体を40度〜70度
の範囲にある蒸着入射角度θにより蒸着を行い電極膜を
形成している。なおここで、原板の主面と金属蒸気流の
上流方向とのなす角度θを蒸着入射角度という。
In the manufacturing method of the above-mentioned prior example, as shown in FIG.
! The electrode film is formed by evaporating the entire substrate including the overlapping portion with 3 at an evaporation incident angle θ in the range of 40 degrees to 70 degrees. Note that the angle θ formed between the main surface of the original plate and the upstream direction of the metal vapor flow is referred to as the evaporation incident angle.

ところが第3図(a)に示す如く蒸着用メタルマスク6
と感vi1素子膜2及び基板1の主面とが密着している
場合であっても蒸着入射角度の傾斜の故に電極膜3と感
磁素子膜2の臣なる部分の大きさが蒸着入射角度の傾斜
方向において異なる。
However, as shown in FIG. 3(a), the metal mask 6 for vapor deposition
Even when the magneto-sensitive element film 2 and the main surface of the substrate 1 are in close contact with each other, the size of the corresponding portion of the electrode film 3 and the magneto-sensitive element film 2 is smaller than the evaporation incidence angle due to the inclination of the evaporation incidence angle. differs in the direction of inclination.

さらには、第3図(a)に示す如く蒸着用メタルマスク
6にギャップ7がある場合には電極膜3が感磁素子ff
12から離れて形成されてしまい、極端な場合には、隣
接する感磁素子膜2に跨がって電極膜3が形成されてし
まう欠点があった。従って、先行例の製造方法による″
と不良品の発生が多く製品の歩留が低いものになってい
た。
Furthermore, if there is a gap 7 in the metal mask 6 for vapor deposition as shown in FIG.
The electrode film 3 is formed apart from the magnetically sensitive element film 12, and in extreme cases, the electrode film 3 may be formed astride the adjacent magnetically sensitive element film 2. Therefore, due to the manufacturing method of the preceding example,
This resulted in a high number of defective products, resulting in low product yields.

発明の概要 そこで、本発明の目的は、製造歩留の良いチップホール
素子の製造方法を提供することである。
SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a method for manufacturing a chip Hall element with a high manufacturing yield.

本発明のチップホール素子の製造方法は、原板に複数の
基板を画定する溝を形成する工程と、基板の各々の主面
に感磁素子膜を形成する蒸着工程と、基板の各々の主面
に形成されかつ感磁素子膜に接続する2対の電極膜を形
成する蒸着工程と、感磁素子膜並びに電極と感磁索子膜
との接続部分を被膜する保護膜を形成する工程とからな
り、当該電極膜を形成する蒸着工程において原板の主面
と金属蒸気流の上流方向とのなす蒸着入射角を変化せし
めることを特徴とするものである。
The method for manufacturing a chip Hall element of the present invention includes a step of forming grooves on an original plate to define a plurality of substrates, a vapor deposition step of forming a magnetically sensitive element film on each main surface of the substrates, and a step of forming a magnetically sensitive element film on each main surface of the substrates. a vapor deposition process for forming two pairs of electrode films formed on the magnetically sensitive element film and connected to the magnetically sensitive element film, and a process for forming a protective film that covers the magnetically sensitive element film and the connecting portion between the electrode and the magnetically sensitive element film. The method is characterized in that the vapor deposition incident angle formed between the main surface of the original plate and the upstream direction of the metal vapor flow is changed in the vapor deposition process for forming the electrode film.

え−LJL 以下、本発明の実施例を図に基づいて説明する。E-LJL Embodiments of the present invention will be described below with reference to the drawings.

第4図は、本発明のチップホール素子の製造方法の実施
例のフローチャートである。
FIG. 4 is a flowchart of an embodiment of the method for manufacturing a chip Hall element of the present invention.

初めに、区画溝付原板準備工程S1においては、例えば
、セラミック等からなる原板5に複数の格子状の基板1
を区画する溝8をダイシングソー等でハーフカットし、
洗浄を行い下地を蒸着して区゛   両溝付原板を用意
する。
First, in the partition grooved original plate preparation step S1, a plurality of lattice-shaped substrates 1 are placed on an original plate 5 made of, for example, ceramic.
Half-cut the groove 8 that divides the
After cleaning and depositing a base, a double-grooved base plate is prepared.

次に、感磁素子膜形成工程S2においては、得られた原
板の主面にメタルマスクによってマスキングを行い、I
nSbを蒸着して感磁索子膜を形成する。
Next, in the magnetosensitive element film forming step S2, the main surface of the obtained original plate is masked with a metal mask, and the I
A magnetically sensitive wire film is formed by depositing nSb.

次の第1電極膜形成工程S3においては、第5図(a)
の概略断面図の如く、蒸着装置内の金属蒸気流の方向に
対してマスキングを施した原板5の主面を然看入射角度
θ好ましくは70〜90度程度に保って該金属蒸気流の
上流方向に向けて、予め感磁素子膜2を形成された基板
1上に第1電極膜3aを蒸着する。第6図(a)の平面
図の如く第1電1!i膜3aは基板1の主面にて感磁素
子膜2と部分的に積属するように形成される。この場合
、第5図(b)に示すようにギャップがある場合でも第
1電FAF!3atfi積居されるべき感磁素子膜2か
らずれて形成されることはない。この第1電極膜形成工
程においてはCrをまず蒸着してCUをその上にv4層
する。また第1電極膜の膜厚は少なくとも0.2μmの
厚さを保ち後に形成される保1fJにより保護される。
In the next first electrode film forming step S3, as shown in FIG.
As shown in the schematic cross-sectional view, the main surface of the original plate 5, which has been masked with respect to the direction of the metal vapor flow in the vapor deposition apparatus, is placed upstream of the metal vapor flow while keeping the incident angle θ preferably at about 70 to 90 degrees. A first electrode film 3a is deposited on the substrate 1 on which the magnetically sensitive element film 2 has been formed in advance. As shown in the plan view of FIG. 6(a), the first electric 1! The i film 3a is formed on the main surface of the substrate 1 so as to partially overlap with the magnetically sensitive element film 2. In this case, even if there is a gap as shown in FIG. 5(b), the first electric FAF! 3atfi will not be formed out of alignment with the magnetically sensitive element film 2 to be deposited. In this first electrode film forming step, Cr is first vapor deposited and CU is formed as a v4 layer thereon. Further, the thickness of the first electrode film is maintained to be at least 0.2 μm and is protected by a protective layer 1fJ formed later.

次に、第2電極膜形成工程S4においては、別のメタル
マスクを用いて開口の位置を変え、蒸着入射角度θが3
0〜60度程度の範囲内に在るように原板5をCuの金
aH気流に対して配置せしめた後、再び蒸着を61始し
て第6図(b)及び第7図(a>に承りように基板1の
主面から溝8′の側面までに亘って第2電極膜3bを蒸
着する。この場合でも、第7図(b)に示す如くギャッ
プ7が在る場合でも予め第1電極膜3aが形成されてい
るので充分なる重なり部分が得られる。Ti極膜3aは
、はんだが電極膜3に良く付着するように電極膜の全体
膜厚がその厚さ1.0μm以上でありかつ基板の主面か
ら側面にかけて形成される。
Next, in the second electrode film forming step S4, the position of the opening is changed using another metal mask, and the deposition incident angle θ is adjusted to 3.
After placing the original plate 5 against the Cu gold aH airflow so that the angle is within the range of about 0 to 60 degrees, the vapor deposition was started again at 61, as shown in FIGS. 6(b) and 7(a). The second electrode film 3b is deposited from the main surface of the substrate 1 to the side surface of the groove 8' as shown in FIG. Since the electrode film 3a is formed, a sufficient overlapping area can be obtained.The Ti electrode film 3a has a total thickness of 1.0 μm or more so that the solder adheres well to the electrode film 3. It is formed from the main surface to the side surface of the substrate.

次に、第1保護膜形成工程S5においては、感磁素子膜
と電極膜との接合部並びに感磁素子膜を保護するために
AQzOzからなる第1保11uをパッシベーションに
よって形成する。
Next, in the first protective film forming step S5, a first protective film 11u made of AQzOz is formed by passivation in order to protect the joint between the magnetically sensitive element film and the electrode film as well as the magnetically sensitive element film.

次いで第2保護膜形成工程S6においては、第1保護膜
の上に樹脂からなる第2保LW膜を積層して、感磁素子
膜と電極膜の接合部及び感磁素子膜を被覆するアルミナ
の下層及び樹脂の上層からなる2層構造の保護膜4を設
ける。
Next, in the second protective film forming step S6, a second protective LW film made of resin is laminated on the first protective film, and an alumina film is formed to cover the joint between the magnetically sensitive element film and the electrode film and the magnetically sensitive element film. A protective film 4 having a two-layer structure consisting of a lower layer of resin and an upper layer of resin is provided.

その後、基板スクライプ工程S7を行う。After that, a substrate scribing step S7 is performed.

そして、はんだ塗布工程S8では、直接プリント配線に
接続させるために電極股上にはんだディプを形成する。
Then, in the solder application step S8, a solder dip is formed on the crotch of the electrode in order to connect it directly to the printed wiring.

その後、得られた原板を区画溝に沿って切り検査工程S
9を経て本発明のチップホール素子が得られる。
After that, the obtained original plate is cut along the dividing grooves in an inspection step S.
The chip Hall element of the present invention is obtained through step 9.

このように電極膜を形成する蒸着工程は電極膜が@磁素
子I! 2に電気的に接続する第1電極II!13aを
形成する第1電楡l!蒸着工程と、第1電極膜に電気的
に接続する第2電極WA3bを形成する第2電極膜蒸セ
工程とにより基板の側面に亘って積層している電極膜を
形成している。第1電極股蒸着工程及び第2電極i*i
a工程における原板の主面を金属蒸気流の上流方向に対
して傾斜させ、第1T1極l!蒸着工程における原板の
主面と金i蒸気流の上流方向とのなす蒸着入射角が第2
1!極膜蒸着工程における蒸着入射角より大となってい
る。
In the vapor deposition process for forming the electrode film in this way, the electrode film is @magnetic element I! The first electrode II electrically connected to 2! The first electrical ridge l forming 13a! An electrode film laminated over the side surface of the substrate is formed by a vapor deposition process and a second electrode film vaporization process for forming a second electrode WA3b electrically connected to the first electrode film. First electrode crotch deposition process and second electrode i*i
The main surface of the original plate in step a is inclined with respect to the upstream direction of the metal vapor flow, and the first T1 pole l! In the vapor deposition process, the vapor deposition incident angle between the main surface of the original plate and the upstream direction of the gold i vapor flow is the second
1! This is larger than the deposition incident angle in the electrode film deposition process.

上記の如く本実施例によればメタルマスク6と感磁素子
膜2及び基板1の主面とが密着している場合でもギャッ
プ7がある場合でも電極膜3と感磁素子膜2の重なる部
分がほぼ同様な広さの面積で形成され、電極1!13と
感磁素子膜2と電気的接続が確実に得られる。
As described above, according to this embodiment, even when the metal mask 6, the magnetically sensitive element film 2, and the main surface of the substrate 1 are in close contact with each other, even when there is a gap 7, the overlapping portion of the electrode film 3 and the magnetically sensitive element film 2 are formed with approximately the same area, and electrical connection between the electrodes 1 and 13 and the magnetically sensitive element film 2 can be reliably obtained.

また、本実施例では第1電極膜から第2電極膜の順に蒸
着形成しているが、第8図(a)及び(b)に示すよう
に第2電極膜3bを先に形成し、その上に第1N極膜3
aを蒸着形成しても良いことは明らかである。
Furthermore, in this embodiment, the first electrode film and the second electrode film are deposited in this order, but as shown in FIGS. 8(a) and (b), the second electrode film 3b is formed first, and then the second electrode film 3b is formed first. First N pole film 3 on top
It is clear that a may be formed by vapor deposition.

効   果 以上の如く、本発明のチップホール素子の製造方法によ
れば、電極膜を形成する蒸着工程において原板の主面と
金属蒸気流の上流方向とのなす蒸着入射角を変化せしめ
ること、例えば蒸着入射角を70度〜90度の範囲から
選ばれる1の角度から30度〜60度の範囲から選ばれ
る他の角度まで変化させることにより、電極膜と感磁素
子膜との重なり部分が必ず得られかつ電極膜を区画溝の
側面に渡って形成することが出来る。
Effects As described above, according to the method for manufacturing a chip Hall element of the present invention, in the vapor deposition process for forming an electrode film, the incident angle of vapor deposition between the main surface of the original plate and the upstream direction of the metal vapor flow can be changed, for example. By changing the deposition incident angle from one angle selected from the range of 70 degrees to 90 degrees to another angle selected from the range of 30 degrees to 60 degrees, it is possible to ensure that the overlapped portion of the electrode film and the magnetically sensitive element film is Thus, an electrode film can be formed over the side surfaces of the partition grooves.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)は先行例のチップホール素子の平面図であ
り、第1図(b)は第1図(a)のI!jlA−Aの断
面図であり、第2図(a)、(b)及び(C)は先行例
であるチップホール素子製造方法の蒸着工程における基
板の概略平面図であり、第3図(a)及び(b)は第2
図(b)の線B−8の概略部分断面図であり、第4図は
本発明のチップホール素子の製造方法を示すフローチャ
ートであり・、第5図(a)及び(b)は第6図(a>
の線C−Cの概略部分断面図であり、第6図(a)は第
1電極wA蒸着工程における原板の部分平面図であり、
第6図(b)は第2電極膜蒸着工程における原板の部分
平面図であり、第7図(a)及び(b)は第6図(b)
の線D−Dの概略部分断面図であり、第8図(a)は第
2電極膜蒸着工程における原板の部分平面図であり、第
8図(b)は第1電極膜蒸着工程における原板の部分平
面図である。 主要部分の符号の説明 1・・・・・・基板 2・・・・・・感磁索子膜  3・・・・・・電極膜4
・・・・・・保護膜    5・・・・・・原板6・・
・・・・メタルマスク 7・・・・・・ギャップ   8・・・・・・溝((1
)   嶌f回   rb+ 簗、3図 鳥4図 襄5図 襄l=凹 16゜ (α) ′  秦7図
FIG. 1(a) is a plan view of the chip Hall element of the prior example, and FIG. 1(b) is the I! of FIG. 1(a). FIG. 2(a), (b) and (C) are schematic plan views of the substrate in the vapor deposition process of the chip Hall element manufacturing method which is a prior example, and FIG. 3(a) is a sectional view of ) and (b) are the second
FIG. 4 is a flowchart showing the method for manufacturing a chip Hall element of the present invention; FIGS. Diagram (a>
FIG. 6(a) is a partial plan view of the original plate in the first electrode wA vapor deposition step;
FIG. 6(b) is a partial plan view of the original plate in the second electrode film deposition step, and FIG. 7(a) and (b) are the same as FIG. 6(b).
FIG. 8(a) is a partial plan view of the original plate in the second electrode film deposition process, and FIG. 8(b) is a partial plan view of the original plate in the first electrode film deposition process. FIG. Explanation of symbols of main parts 1... Substrate 2... Magnetically sensitive cable membrane 3... Electrode film 4
......Protective film 5...Original plate 6...
...Metal mask 7...Gap 8...Groove ((1
) Shima f times rb+ Yan, 3rd figure bird 4th figure 5th figure 6th l = concave 16° (α) ′ Qin 7th figure

Claims (3)

【特許請求の範囲】[Claims] (1)原板に複数の基板を画定する溝を形成する工程と
、前記基板の各々の主面に感磁素子膜を形成する蒸着工
程と、前記基板の各々の主面に形成されかつ前記感磁素
子膜に接続する2対の電極膜を形成する蒸着工程と、前
記感磁素子膜並びに前記電極と前記感磁素子膜との接続
部分を被膜する保護膜を形成する工程とからなり、前記
電極膜を形成する蒸着工程において前記原板の主面と前
記金属蒸気流の上流方向とのなす蒸着入射角を変化せし
めることを特徴とするチップホール素子の製造方法。
(1) A step of forming grooves on an original plate to define a plurality of substrates; a vapor deposition step of forming a magnetically sensitive element film on each main surface of the substrate; The step includes a vapor deposition step of forming two pairs of electrode films connected to the magnetic element film, and a step of forming a protective film covering the magnetically sensitive element film and the connecting portion between the electrode and the magnetically sensitive element film, 1. A method for manufacturing a chip Hall element, characterized in that in a vapor deposition step for forming an electrode film, an incident angle of vapor deposition between the main surface of the original plate and the upstream direction of the metal vapor flow is changed.
(2)前記電極膜を形成する蒸着工程は第1電極膜蒸着
工程と第2電極膜蒸着工程とからなり前記第1電極膜蒸
着工程における蒸着入射角と第2電極膜蒸着工程におけ
る蒸着入射角とを異ならしめることを特徴とする特許請
求の範囲第1項記載の製造方法。
(2) The vapor deposition process for forming the electrode film includes a first electrode film vapor deposition process and a second electrode film vapor deposition process, and the vapor deposition incident angle in the first electrode film vapor deposition process and the vapor deposition incident angle in the second electrode film vapor deposition process. 2. The manufacturing method according to claim 1, wherein:
(3)前記第1電極膜蒸着工程における前記蒸着入射角
は70度〜90度の範囲にあり、前記第2電極膜蒸着工
程における前記蒸着入射角は30度〜60度の範囲にあ
ることを特徴とする特許請求の範囲第2項記載の製造方
法。
(3) The vapor deposition incident angle in the first electrode film vapor deposition step is in the range of 70 degrees to 90 degrees, and the vapor deposition incident angle in the second electrode film vapor deposition step is in the range of 30 degrees to 60 degrees. A manufacturing method according to claim 2, characterized in that:
JP59181502A 1984-08-30 1984-08-30 Production of chip hall element Pending JPS6159786A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59181502A JPS6159786A (en) 1984-08-30 1984-08-30 Production of chip hall element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59181502A JPS6159786A (en) 1984-08-30 1984-08-30 Production of chip hall element

Publications (1)

Publication Number Publication Date
JPS6159786A true JPS6159786A (en) 1986-03-27

Family

ID=16101876

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59181502A Pending JPS6159786A (en) 1984-08-30 1984-08-30 Production of chip hall element

Country Status (1)

Country Link
JP (1) JPS6159786A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04227090A (en) * 1990-06-27 1992-08-17 Hughes Aircraft Co Method for reducing irregularity of coated surface by means of electrostatic pressure

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04227090A (en) * 1990-06-27 1992-08-17 Hughes Aircraft Co Method for reducing irregularity of coated surface by means of electrostatic pressure

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