JPS6158036A - 乗算器 - Google Patents

乗算器

Info

Publication number
JPS6158036A
JPS6158036A JP59179638A JP17963884A JPS6158036A JP S6158036 A JPS6158036 A JP S6158036A JP 59179638 A JP59179638 A JP 59179638A JP 17963884 A JP17963884 A JP 17963884A JP S6158036 A JPS6158036 A JP S6158036A
Authority
JP
Japan
Prior art keywords
output
supplied
sum
carry
multiplier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59179638A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0326857B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html
Inventor
Noriyuki Ikumi
幾見　宣之
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP59179638A priority Critical patent/JPS6158036A/ja
Publication of JPS6158036A publication Critical patent/JPS6158036A/ja
Publication of JPH0326857B2 publication Critical patent/JPH0326857B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/533—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even
    • G06F7/5334—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product
    • G06F7/5336—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product overlapped, i.e. with successive bitgroups sharing one or more bits being recoded into signed digit representation, e.g. using the Modified Booth Algorithm
    • G06F7/5338—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product overlapped, i.e. with successive bitgroups sharing one or more bits being recoded into signed digit representation, e.g. using the Modified Booth Algorithm each bitgroup having two new bits, e.g. 2nd order MBA

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Multi Processors (AREA)
  • Image Processing (AREA)
JP59179638A 1984-08-29 1984-08-29 乗算器 Granted JPS6158036A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59179638A JPS6158036A (ja) 1984-08-29 1984-08-29 乗算器

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59179638A JPS6158036A (ja) 1984-08-29 1984-08-29 乗算器

Publications (2)

Publication Number Publication Date
JPS6158036A true JPS6158036A (ja) 1986-03-25
JPH0326857B2 JPH0326857B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1991-04-12

Family

ID=16069263

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59179638A Granted JPS6158036A (ja) 1984-08-29 1984-08-29 乗算器

Country Status (1)

Country Link
JP (1) JPS6158036A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5060183A (en) * 1987-11-19 1991-10-22 Mitsubishi Denki Kabushiki Kaisha Parallel multiplier circuit using matrices, including half and full adders
FR2662829A1 (fr) * 1990-05-31 1991-12-06 Samsung Electronics Co Ltd Multiplicateur parallele utilisant un reseau de saut et un arbre de wallace modifie.
JP2010165179A (ja) * 2009-01-15 2010-07-29 Hiroshima Univ 半導体装置

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5856033A (ja) * 1981-09-29 1983-04-02 Fujitsu Ltd 乗算回路

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5856033A (ja) * 1981-09-29 1983-04-02 Fujitsu Ltd 乗算回路

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5060183A (en) * 1987-11-19 1991-10-22 Mitsubishi Denki Kabushiki Kaisha Parallel multiplier circuit using matrices, including half and full adders
FR2662829A1 (fr) * 1990-05-31 1991-12-06 Samsung Electronics Co Ltd Multiplicateur parallele utilisant un reseau de saut et un arbre de wallace modifie.
JP2010165179A (ja) * 2009-01-15 2010-07-29 Hiroshima Univ 半導体装置

Also Published As

Publication number Publication date
JPH0326857B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1991-04-12

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