JPS6157732U - - Google Patents
Info
- Publication number
- JPS6157732U JPS6157732U JP14303484U JP14303484U JPS6157732U JP S6157732 U JPS6157732 U JP S6157732U JP 14303484 U JP14303484 U JP 14303484U JP 14303484 U JP14303484 U JP 14303484U JP S6157732 U JPS6157732 U JP S6157732U
- Authority
- JP
- Japan
- Prior art keywords
- counting
- bits
- frame
- information
- logic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Detection And Prevention Of Errors In Transmission (AREA)
- Transmission Systems Not Characterized By The Medium Used For Transmission (AREA)
Description
第１図ないし第３図はこの考案のデジタル情報
信号処理装置の１実施例を示し、第１図はブロツ
ク図、第２図ａ〜ｃ、第３図ａ〜ｃは第１図の動
作説明用のタイミングチヤート、第４図はアナロ
グ信号のＰＣＭ変調の説明用波形図、第５図はデ
ジタル情報信号の基本構成のフオーマツト、第６
図ａ，ｂは衛星テレビジヨン放送の音声方式のＡ
，Ｂモードに適用されるデジタル情報信号のフオ
ーマツトである。
２…シフトレジスタ、３ａ〜３ｐ…アンドゲー
ト、５ａ〜５ｐ…カウンタ、６ａ〜６ｐ…フリツ
プフロツプ。
1 to 3 show one embodiment of the digital information signal processing device of this invention, FIG. 1 is a block diagram, and FIGS. 2 a to c, and 3 a to c are explanations of the operation of FIG. 1. Figure 4 is a waveform diagram for explaining PCM modulation of an analog signal, Figure 5 is a format of the basic configuration of a digital information signal, and Figure 6 is a timing chart for explaining the PCM modulation of an analog signal.
Figures a and b are audio format A for satellite television broadcasting.
, the format of the digital information signal applied to B mode. 2...Shift register, 3a-3p...AND gate, 5a-5p...counter, 6a-6p...flip-flop.
Claims (1)
御情報などの特定情報に割り当てられたデジタル
情報信号を受信または再生処理するデジタル情報
信号処理装置において、受信または再生されたデ
ジタル情報信号の各フレームのＰビツトを１ビツ
トづつ順次に書き換え保持する入力側情報保持手
段と、フレーム毎に前記保持手段に保持された前
記所定位置のＰビツトを転送する転送制御手段と
、該転送制御手段により転送された前記所定位置
のＰビツトが１ビツトづつ個別に入力されるとと
もに前記特定情報の内容が同一に保持される期間
より十分短いＭフレーム毎に転送されたＭフレー
ムの前記所定位置のＰビツトの各１ビツトがそれ
ぞれ論理１または０になるフレーム数を計数する
Ｐ個のカウンタを有し、該各カウンタの計数値そ
れぞれＭ／２より大、Ｍ／２以下により各ビツト
が前記各カウンタの計数論理、該論理の反転論理
になるＰビツトの計数信号を出力する計数手段と
、前記各カウンタのＭフレームの計数が終了する
毎に前記計数信号を書き換え保持し、前記特定情
報をＭフレーム毎に多数決処理して形成した多数
決判別情報を出力する出力側情報保持手段とを備
えたデジタル情報信号処理装置。 In a digital information signal processing device that receives or reproduces a digital information signal in which P bits at a predetermined position of each frame in a time series are assigned to specific information such as control information, each frame of the received or reproduced digital information signal is input-side information holding means for sequentially rewriting and holding P bits one by one; transfer control means for transferring the P bits at the predetermined positions held in the holding means for each frame; Each of the P bits at the predetermined position of the M frame is transferred every M frame, which is sufficiently shorter than the period during which the P bits at the predetermined position are individually input one by one and the content of the specific information is kept the same. It has P counters that count the number of frames in which each bit becomes logic 1 or 0, and each bit is determined by the counting logic of each counter when the count value of each counter is greater than M/2 and less than or equal to M/2, a counting means for outputting a P-bit counting signal having an inverted logic of the logic; and a counting means for rewriting and holding the counting signal every time the counting of M frames of each counter is completed, and majority voting processing for the specific information every M frames. and output-side information holding means for outputting majority decision information formed by the digital information signal processing apparatus.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1984143034U JPH042516Y2 (en) | 1984-09-20 | 1984-09-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1984143034U JPH042516Y2 (en) | 1984-09-20 | 1984-09-20 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6157732U true JPS6157732U (en) | 1986-04-18 |
| JPH042516Y2 JPH042516Y2 (en) | 1992-01-28 |
Family
ID=30701347
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1984143034U Expired JPH042516Y2 (en) | 1984-09-20 | 1984-09-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH042516Y2 (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5329644A (en) * | 1976-08-31 | 1978-03-20 | Nec Corp | Detecting circuit for data signal |
| JPS5741051A (en) * | 1980-08-22 | 1982-03-06 | Mitsubishi Electric Corp | Voice muting circuit |
-
1984
- 1984-09-20 JP JP1984143034U patent/JPH042516Y2/ja not_active Expired
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5329644A (en) * | 1976-08-31 | 1978-03-20 | Nec Corp | Detecting circuit for data signal |
| JPS5741051A (en) * | 1980-08-22 | 1982-03-06 | Mitsubishi Electric Corp | Voice muting circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH042516Y2 (en) | 1992-01-28 |
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