JPH042516Y2 - - Google Patents

Description

[Detailed explanation of the idea]

[Industrial Application Field] This invention relates to a digital information signal processing device that receives or reproduces digital information signals formed based on the audio signal system of satellite television broadcasting. [Conventional technology] Conventionally, in satellite television broadcasting, analog audio signals are encoded using PCM modulation, and
It has been proposed to transmit using a frame transmission method. By the way, analog signals such as audio signals are transmitted at fixed time intervals as shown in Figure 4.
At the same time as sampling at T _s , the time series sampling values obtained by this sampling are
PCM modulation is performed by converting each signal into a binary code with N quantization bits using a D converter or the like. In addition, when digitally transmitting or digitally recording time-series transmission information such as audio information formed by PCM modulation of an analog signal using a frame transmission method, the time-series transmission information is transmitted every frame, that is, a predetermined S sample. At the same time, synchronization information, the content of the transmitted information, P-bit control information indicating the control method, etc., and information for error detection or error correction are added to each frame of transmitted information, and then transmitted, received, or recorded/played. Each frame of a digital information signal is formed. In each frame of the digital information signal, basically, as shown in Fig. 5, a storage section for synchronization information, control information, transmission information for S samples, and information for error detection or error correction is located in order from the beginning. do. Then, the digital information signal is transmitted frame by frame from the transmitting side to the receiving side via a propagation medium such as radio waves, resulting in digital transmission of analog signals such as audio signals, and digital information signals are transferred to magnetic tapes, magnetic disks, etc. Digital recording of analog signals such as audio signals is performed by recording frame by frame on a recording medium such as . By the way, in the case of the audio signal system for satellite television broadcasting, see Broadcasting Technology (Volume 36, 4, 1983), 132~
“Audio signal system for satellite television broadcasting” on page 137
(Author: Yoshiyuki Takeda), audio signals are encoded into A and B modes based on audio quality standards to form time-series audio information to be transmitted. Note that in the A mode, the audio signal is encoded into a 10-bit audio signal, and in the B mode, the audio signal is encoded into 16-bit audio information. Furthermore, in A mode, each frame of the digital information signal can transmit 32 samples of 4 channels of audio information formed by encoding 4 channels of audio signals, and in B mode, Each frame of the digital information signal makes it possible to transmit 48 samples of two channels of audio information formed by encoding two channels of audio signals. Note that the 4-channel and 2-channel audio signals are composed of either a stereo audio signal, a stereo audio signal and a monaural audio signal, or a monaural audio signal. And each frame of digital information signal is 2048
In addition, in A mode, as shown in FIG. 6a, 16-bit frame synchronization information, control information, and audio information to be transmitted, which correspond to the synchronization information and control information in FIG. 5, in order from the beginning. 32-bit range bit indicating degree of compression, 4
Audio information for one frame of a channel, i.e.
128 samples of audio information, 480 bits of independent information,
A storage section for 7 x 32 bit error detection and correction information is located. In addition, in B mode, as shown in FIG. 6b, 16-bit frame synchronization information corresponding to the synchronization information and control information in FIG. 5 in order from the beginning,
Storage of control information, 16 bits of range bits, 16 bits of independent information, audio information for one frame of two channels, i.e. 96 samples of audio information, 224 bits of independent information, and 7 x 32 bits of error detection and correction information. Department is located. In other words, the digital information signal formed based on the audio signal system of satellite television broadcasting is
Regardless of the mode, P=16 bits located at a predetermined position in each frame, that is, the 17th to 32nd bits, are assigned to control information, which is specific information. And the 1st to 16th bits of control information ~
Logic 1 or 0 (hereinafter, logic 1 and 0 are referred to as “1” and “0”)
) is set based on the control details in the table below, and the first bit indicates the A or B mode, and the combination of the second and third bits indicates the control for the two-channel audio information storage section. Stereo, monaural 1 channel, and monaural 2 channels are indicated, and depending on the combination of the 4th and 5th bits, stereo, monaural 1 channel, and monaural 2 channels are determined for the audio information storage unit of the remaining 2 channels in A mode. The difference is shown.

【table】

[Problem that the invention attempts to solve]

By the way, if the received control information is used as it is to perform the grasping, etc., there is a problem that if the reception condition deteriorates and the probability of a code error in the received control information, that is, the specific information, increases, the above grasping, etc. cannot be carried out accurately. There is. SUMMARY OF THE INVENTION An object of the present invention is to provide a digital information signal processing device that obtains correct specific information through simple majority voting processing. [Means for solving the problem] This invention provides a digital information signal processing device that receives or reproduces a digital information signal in which P bits at a predetermined position of each frame in a time series are assigned to specific information such as control information. , the received or reproduced digital information signal of each frame is moved one bit at a time to the next stage and P bits are held at a time.
one shift register having a stage configuration; a transfer control means having a gate circuit configuration that extracts only the P bits at the predetermined position held in the shift register for each frame; and the contents of the specific information are held the same. Repeat counting the number of frames in which each of the P bits at the predetermined position becomes logical 1 or 0 between predetermined M frames that are sufficiently shorter than the period, and if the count value between the M frames is greater than M/2 and less than M/2. P counters that output a count signal that changes in binary; and P flip-flops that output P bits of the majority vote processing result for each M frame of the specific information by setting and resetting each counter based on the count signal of each counter. This is a digital information signal processing device comprising: [Function] In the case of the digital information signal processing device of the present invention configured as described above, one small-capacity shift register that holds only P bits in one frame and transfer control means having a gate circuit configuration provide the following effects. Regardless of the number of bits in one frame, P bits at the position of specific information of the digital information signal of each frame are extracted. Furthermore, for each extracted P bit,
Counting of the number of logical 1 or 0 frames between M frames set by P counters is repeated, and by a majority of the counting results of the number of frames, 2
A counting signal whose value changes is output from each counter. Then, P flip-flops are set or reset by the count signal of each counter, and P bits of specific information are formed and outputted by each flip-flop based on majority processing among M frames. In this case, the specific information is determined based on majority voting for the P bits at the position of the specific information extracted from each frame for each M frame in which the content of the specific information does not change. It becomes possible to accurately grasp the content of specific information received or reproduced. Moreover, the P bits at the specific information position of each frame are extracted by a small-capacity shift register and a transfer control means with a simple gate circuit configuration, and
The majority voting process for each M frame of each extracted P bit is performed using P counters that count the number of logical 1 or 0 frames for each bit and M frames for each counter.
This is carried out with a simple structure consisting of P flip-flops that are set or reset according to the counting result for each frame. [Embodiment] Next, this invention will be explained in detail with reference to the drawings of FIGS. 1 to 3 showing one embodiment of the invention. The present invention is applied to a digital information signal processing device consisting of a receiver for satellite television broadcasting, and the processing circuit shown in FIG. 1 is provided in the device. By the way, in the audio signal system of satellite television broadcasting, as shown in FIG. Bits are assigned to control information which is specific information, for example M=15
The contents of the control information are kept the same for a short period of time, such as a frame. In the case of satellite television broadcasting, the digital information signal is modulated and transmitted, so the received digital information signal is formed by demodulating the received signal, and the received digital information is The signal is sequentially input one bit at a time via the reception input terminal 1 to a 16-bit (16 stage) shift register 2 which forms the input side information holding means, and at this time, based on the frame synchronization signal of the received digital information signal, etc. A clock signal of the clock input terminal 2' formed internally in the shift register 2, that is, a clock signal that rises at the center of each bit of the received digital information signal, is input to the shift register 2, and based on the clock signal, the received digital information signal is The bits in the shift register 2 are sequentially moved to the next stage, and the received 1 bit is transferred to the shift register 2.
Each frame's digital information signal is held in 16-bit units in the order in which they were received. Further, the shift register 2 has output terminals q ₁ , ..., q ₁₅ , q ₁₆ at each of the first to 16th stages, and the second
As shown in Figure a, during the control information period T, the position of the control information of the received digital information signal of each frame is
Retains 16 bits. Then, when the last bit of the control information is taken into the shift register ₂ at time ta based on the clock signal shown in _FIG . Each bit is output. And each output terminal q ₁ to _{q 16} of shift register 2
16 AND gates forming the transfer control means, that is, the first to 16th AND gates 3a, 3b,
. . . 3p, and is connected to the other input terminal of each AND gate 3a to 3p. As shown in Figure 2c, a latch pulse that rises at time ta', which is a little after the rising edge ta of the last clock signal in period T, is input.
Based on the latch pulse, each bit of the control information of each frame held in the shift register 2 is extracted from each AND gate 3a to 3p, respectively. By the way, when the received digital information signal consists of a digital information signal of a B-mode stereo audio signal, if the transmission condition is good and there is no code error, based on the above table, for example, the first bit of the control information is "1" and the first bit is "1". 2. Both the third bit becomes “0”,
At this time, the output of the first AND gate 3a is "1",
The output of the second AND gate 3a becomes "0", but if the transmission condition is bad and there is a code error, the output of the first AND gate 3a becomes "0" or the output of the second AND gate 3a becomes "0".
The output of b becomes "1". Further, the latch pulse is output only at time ta' of each frame, and the output of each AND gate 3a to 3p becomes "1" in each frame except when all bits of control information are held in the shift register 2.
It never becomes. The outputs of the AND gates 3a to 3b form a first counter consisting of a four-stage binary counter and forming a counting means.
or 16th counters 5a, 5b, ..., 5p, respectively, and each counter 5
For a to 5p, each time the clock terminal k becomes "1", the count value is increased by one. Therefore, each of the counters 5a to 5p counts the number of frames in which each bit of the control information becomes "1", and at this time, a clear pulse to be described later is applied to the clear terminal cl of each of the counters 5a to 5p, that is, M=15 frames. Since a clear pulse is input every time reception is completed, each of the counters 5a to 5p counts the number of frames that become "1" every M=15 frames of the received digital information signal. Furthermore, only when the fourth bit output terminal of each counter 5a to 5p, that is, the count value is 8 or more, is "1".
The first to sixteenth flip-flops 6a, 6 whose output terminals qd form output-side information holding means
b, . . . , 6p are connected to set terminals s. And the output terminal qd of each counter 5a to 5p is
Each counter 5 becomes "1" only when the counted number of frames is 8 or more, which is greater than M/2.
“1” when the number of frames counted from a to 5p to each flip-flop 6a to 6p is greater than M/2;
Each bit of the 16-bit count signal, which becomes "0" when the count is less than M/2, is output. Further, each of the flip-flops 6a to 6p is set when a "1" bit is input to the set terminal s, and the output from the output terminal q becomes "1". Therefore, the first to sixteenth majority decision information output terminals 7a, 7 are output from each flip-flop 6a to 6p.
b, ..., 7p, in 15 control information during M = 15 frames of the received digital information signal,
When the number of frames that become "1" is 8 or more, which is larger than M/2, "1" is output, and when it is less than M/2, that is, 7 or less, bit data that becomes "0" is output. At this time, the bit data of output terminals 7a to 7p The bit data forms 16 bits of the majority decision processing result of the control information for 15 frames of the received digital information signal, and the majority decision information formed by these 16 bits is output. By the way, the reset terminal r of each flip-flop 6a to 6p receives the reset pulse of the reset input terminal 8, that is, as shown in FIG.
Every time 15 latch pulses are output, a reset pulse is input which rises at time ta'', which is a little later than the rising edge ta' of the 15th latch pulse, and each flip-flop 6a to 6p is reset by this reset pulse, and each output The output of the majority decision information signal to the terminals 7a to 7p is stopped.
[2], ..., [15] indicate the 1st, 2nd, ..., 15th latch pulses. Also, from the clear input terminal 9, each counter 5a~
As shown in Figure 3c, a clear pulse that rises at ta a little later than the rising edge ta'' of the reset pulse is input to the clear terminal cl of 5p, and the counting contents of each counter 5a to 5p are cleared by this clear pulse. Therefore, each flip-flop 6a to 6p
transmits each bit data of majority decision information newly formed by majority decision processing to each output terminal 7a to 7p every 15 frames of the received digital information signal.
Output to. Even if a code error occurs in the control information of frames 1 to 7 of the 15 frames, the majority decision information at the output terminals 7a to 7p becomes control information formed by eliminating the code error, and with this information, Even if the probability of code errors increases, it becomes possible to accurately grasp the contents of the control information. At this time, a small-capacity shift register 2 with a 16-stage configuration that holds only P=16 bits in one frame and AND gates 3a to 3 as transfer control means are used.
16 bits of the control information period T of each frame are extracted by p, and M=15 for the 16 bits extracted by simple majority voting using 16 counters 5a to 5p and flip-flops 6a to 6p.
A majority decision process is performed for each frame, and correct control information can be obtained by the simple majority decision process. Note that the smaller the number of M, the faster the majority decision processing is performed, and the larger the number of M, the more accurate the majority decision processing is performed. In the embodiment, each counter 5a to 5p
Although the number of frames in which each bit of the control information becomes "1" is counted, it goes without saying that the number of frames in which each bit of the control information becomes "0" may also be counted. Further, even if the number of bits of control information is increased or decreased or M is changed, the configuration may be substantially the same as that shown in FIG. 1. Furthermore, it goes without saying that the present invention can be applied not only to received digital information signals, but also to digital information signals reproduced from recording media, for example. [Effects of the Invention] Therefore, the digital information signal processing device of this invention includes one small-capacity shift register that holds only P bits in one frame and transfer control means having a gate circuit configuration. P counters that repeatedly count the number of logical 1 or 0 frames between the set M frames and output a count signal that changes in binary depending on the majority of the count results, and are set or reset by the count signal of each counter. Since it is equipped with P flip-flops that output P bits of specific information based on majority voting among M frames, a small-capacity shift register and a simple gate circuit that hold only the P bits of specific information in each frame are required. The transfer control means of the configuration extracts the necessary P bits of each frame, and also includes P counters that count the number of frames in which each P bit is logical 1 or 0, and M of each counter.
With a simple configuration consisting of P flip-flops that are set or reset according to the counting results for each frame, majority decision processing can be performed for each M frame.
The content of specific information that has been received or reproduced can be accurately grasped, regardless of the state of reception or reproduction, by a simple majority decision process.

[Brief explanation of the drawing]

1 to 3 show one embodiment of the digital information signal processing device of this invention, FIG. 1 is a block diagram, and FIGS. 2 a to c, and 3 a to c are explanations of the operation of FIG. 1. Figure 4 is a waveform diagram for explaining PCM modulation of an analog signal, Figure 5 is a format of the basic configuration of a digital information signal, and Figure 6 is a diagram of the basic configuration of a digital information signal.
Figures a and b show the formats of digital information signals applied to A and B modes of the audio system of satellite television broadcasting. 2...Shift register, 3a-3p...AND gate, 5a-5p...Counter, 6a-6p...
…flipflop.

Claims (1)

[Claims for Utility Model Registration] P bits at predetermined positions of each frame in a time series are received or reproduced by a digital information signal processing device that receives or reproduces a digital information signal assigned to specific information such as control information. one shift register with a P-stage configuration that moves the digital information signal of each frame one bit at a time to a later stage and holds each P bit; transfer control means of the gate circuit configuration to be extracted, and counting the number of frames in which each of the P bits at the predetermined position becomes logical 1 or 0 between predetermined M frames that are sufficiently shorter than the period during which the content of the specific information is held the same. P counters that output count signals that change in binary depending on the count value between the M frames being greater than M/2 and less than or equal to M/2; and setting and resetting based on the count signal of each of the counters. and P flip-flops for outputting P bits of the majority vote processing result for each M frame of the specific information.