JPS6157725U - - Google Patents

Info

Publication number
JPS6157725U
JPS6157725U JP14250484U JP14250484U JPS6157725U JP S6157725 U JPS6157725 U JP S6157725U JP 14250484 U JP14250484 U JP 14250484U JP 14250484 U JP14250484 U JP 14250484U JP S6157725 U JPS6157725 U JP S6157725U
Authority
JP
Japan
Prior art keywords
frequency
subtracting
channel selection
selection device
amplifier circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14250484U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP14250484U priority Critical patent/JPS6157725U/ja
Publication of JPS6157725U publication Critical patent/JPS6157725U/ja
Pending legal-status Critical Current

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  • Superheterodyne Receivers (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の選局装置を示すブロツク図、第
2図はこの考案の一実施例の選局装置を示すブロ
ツク図、第3図はこの考案の動作を説明する線図
である。 1…フロントエンド、2…IF増幅回路、3…
選局回路、4…メモリー、5…レベル検出回路、
6…表示回路。
FIG. 1 is a block diagram showing a conventional channel selection device, FIG. 2 is a block diagram showing a channel selection device according to an embodiment of this invention, and FIG. 3 is a diagram illustrating the operation of this invention. 1...Front end, 2...IF amplifier circuit, 3...
Tuning circuit, 4...memory, 5...level detection circuit,
6...Display circuit.

Claims (1)

【実用新案登録請求の範囲】 (1) スーパーへテロダイン受信機において、I
F増幅回路の出力レベルを検出する手段と、この
出力レベルを記憶する手段と、アンテナ段の同調
周波数に対して2倍の中間周波数を加算および減
算する手段と、この場合のIF増幅回路の出力レ
ベルを比較する手段と、この比較の結果でイメー
ジ周波数による受信であることを表示する手段と
を備えた選局装置。 (2) 局部発振周波数に対して2倍の中間周波数
を加算および減算する手段を設け、イメージ周波
数による受信表示の手段を設けない実用新案登録
請求の範囲第1項記載の選局装置。
[Claims for utility model registration] (1) In a superheterodyne receiver, I
means for detecting the output level of the F amplifier circuit, means for storing this output level, means for adding and subtracting an intermediate frequency twice the tuning frequency of the antenna stage, and an output of the IF amplifier circuit in this case. A channel selection device comprising means for comparing levels and means for displaying the result of the comparison as reception based on the image frequency. (2) The channel selection device according to claim 1, which is provided with means for adding and subtracting an intermediate frequency twice the local oscillation frequency, and does not include means for displaying reception based on an image frequency.
JP14250484U 1984-09-19 1984-09-19 Pending JPS6157725U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14250484U JPS6157725U (en) 1984-09-19 1984-09-19

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14250484U JPS6157725U (en) 1984-09-19 1984-09-19

Publications (1)

Publication Number Publication Date
JPS6157725U true JPS6157725U (en) 1986-04-18

Family

ID=30700828

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14250484U Pending JPS6157725U (en) 1984-09-19 1984-09-19

Country Status (1)

Country Link
JP (1) JPS6157725U (en)

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