JPH02141133U - - Google Patents

Info

Publication number
JPH02141133U
JPH02141133U JP4959089U JP4959089U JPH02141133U JP H02141133 U JPH02141133 U JP H02141133U JP 4959089 U JP4959089 U JP 4959089U JP 4959089 U JP4959089 U JP 4959089U JP H02141133 U JPH02141133 U JP H02141133U
Authority
JP
Japan
Prior art keywords
signal level
pll circuit
received signal
receiver
level detector
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4959089U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP4959089U priority Critical patent/JPH02141133U/ja
Publication of JPH02141133U publication Critical patent/JPH02141133U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Superheterodyne Receivers (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図乃び第2図は、この考案に係るPLL回
路の故障検出装置の実施例を示し、第1図はブロ
ツク図、第2図は受信信号レベルとPLL回路の
動作を示した特性図である。第3図は従来例のブ
ロツク図である。 主な符号の説明、1……受信アンテナ、2……
高周波増幅器、3……PLL回路、4……受信信
号レベル検出器、5……受信信号レベル検出の出
力端子、6……PLLロツク検出の出力端子。
1 and 2 show an embodiment of the failure detection device for a PLL circuit according to this invention, FIG. 1 is a block diagram, and FIG. 2 is a characteristic diagram showing the received signal level and the operation of the PLL circuit. It is. FIG. 3 is a block diagram of a conventional example. Explanation of main symbols, 1...Receiving antenna, 2...
High frequency amplifier, 3... PLL circuit, 4... Received signal level detector, 5... Output terminal for receiving signal level detection, 6... Output terminal for PLL lock detection.

Claims (1)

【実用新案登録請求の範囲】 受信機のPLL回路のロツクアウトにおいて、 受信機に設けられた受信信号レベル検出器と、
この受信信号レベル検出器の検出信号によつてP
LL回路のロツクアウト動作を判断する判断手段
とで構成したことを特徴とするPLL回路の故障
検出装置。
[Claims for Utility Model Registration] In locking out the PLL circuit of the receiver, a received signal level detector provided in the receiver;
By the detection signal of this received signal level detector, P
1. A failure detection device for a PLL circuit, comprising a determining means for determining a lockout operation of the LL circuit.
JP4959089U 1989-04-28 1989-04-28 Pending JPH02141133U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4959089U JPH02141133U (en) 1989-04-28 1989-04-28

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4959089U JPH02141133U (en) 1989-04-28 1989-04-28

Publications (1)

Publication Number Publication Date
JPH02141133U true JPH02141133U (en) 1990-11-27

Family

ID=31567412

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4959089U Pending JPH02141133U (en) 1989-04-28 1989-04-28

Country Status (1)

Country Link
JP (1) JPH02141133U (en)

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