JPS6156549A - Signal monitor method - Google Patents

Abstract

PURPOSE:To simplify the constitution of a monitor circuit by deciding a signal fault in a case that a state where ''1'' or ''0'' is delivered at a time from all signal lines is not detected for a fixed period or longer. CONSTITUTION:An AND circuit 1 secures the AND of data lines D1-D4; while an AND circuit 3 secures the AND of the output of an inverter. A 1-shot multi- vibrator MV detects the fall 7 of the output (a) of the circuit 1 and tries to deliver ''0'' for the fixed period T. However this output is kept ''0'' if another fall 8 is produced again during the period T. In the same way, the output of an MV5 is also set at ''0'' in a state where lines D1-D4 deliver all ''0''. As a result, the output (d) of the MV5 is set at ''1'' when the period T passes from a fall 11 produced immediately before the generation of a fault in a case that the output of a certain data line is set continuously at ''1''. Then the output (e) of an OR circuit 6 is also set at ''1''. A case where the output of a certain data line is continuously set at ''0'' is also in the same way.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a signal monitoring method for monitoring whether binary signals of "1" and "0" are normally propagated through a plurality of signal lines.

The present invention is applied, for example, to a circuit that detects a pulse break in a data line in a digital wireless transmission system.

[Prior Art] Conventionally, pulse interruption detection in data lines in digital wireless transmission systems involves full-wave rectification or integration of each signal of a plurality of data lines to be monitored, and detects whether the signal falls within a predetermined range. , depending on whether the signal is a series of "0" or "1".

[Problem that the invention seeks to solve]

However, according to the above conventional method, 16-value QAM
, 64-value digital wireless transmission systems such as 64-value QAM have problems in that the number of signal lines to be monitored increases, the amount of hardware used in the monitoring circuit increases, and the cost increases.

Means for Solving Problem C] In the present invention, in order to solve the above problem, binary signals of "1" and "0" are transmitted normally to a plurality of signal lines. In a signal monitoring method that monitors whether the signal is lIm, or if a state in which "O" is output simultaneously from all the signal lines is not detected for a certain period of time or more, it is determined that the signal is abnormal.

[Effect]

In the present invention, in the case of a normal signal, "1" is generated almost randomly.
or "0" is output, so if the above fixed period is long enough, a state in which "1" is output simultaneously from all signal lines will always be detected within a certain period, and "0" will be output from all signal lines. ” is detected within a certain period of time, and is used to detect an abnormality in the signal. In other words, if the signal from a certain signal line becomes a continuous "0" due to an abnormality in the signal line, the signal will not be detected because "1" is output simultaneously from all signal lines for a certain period of time or more. In addition, even if the signal from a certain signal line becomes a continuous "1", the signal is not detected because "0" is output simultaneously from all signal lines for a certain period of time or more. It is determined that this is an abnormality.

〔Example〕

The present invention will be explained below according to examples.

FIG. 1 is a block diagram of a signal monitoring system according to an embodiment of the present invention, where 1 is a first AND circuit that takes the AND of four data lines, and 2 is a circuit that inverts the polarity of each data line. 3 is a second AND circuit that takes the AND of the outputs from each inverter 2; 4 and 5 are respectively The first and second one-shot multi-byte breaks fall and rise after a certain period of time (T), and 6 is an OR circuit that takes the logical sum of the outputs of the first and second one-shot multi-bye breaks. In addition, Fig. 2 shows Fig. 1 (a) to te.
It is a time chart of each point of l.

During normal operation, almost random signals are input to the data lines D7 to D, so the data lines D7 to D- are all “1”.
'' occurs with a probability of approximately 1/24. Therefore, the first AND circuit 1 outputs ``1'' every 24 bits on average, as shown in FIG. 2(a).

The first one-shot multi-by-break 4 detects the fall 7 of the output of the first AND circuit 1 from "1" to "0", and outputs "0" for a certain period of time (T) from that point. , it tries to rise, but if T (Fig. 2 (dotted line b1) is long enough, falling 8 will occur again during that time, so the rising point will be postponed, and in the end, the output of the first one-shot multi-by-break 4 will be It remains “0”. Similarly, ~D.

Since the state in which all outputs "0" occurs with the probability of 1/2'I, the output of the second one-shot multi-by-break 5 also remains "0".

An abnormality has occurred in the data line, and the output of a certain data line is “1”.
”, the output of the second AND circuit 3 (since C1 remains “O”, the output of the second one-shot multi-by-break 5 is Td in Figure 2). A certain period (T)f&
becomes "1", and the output of the OR circuit 6 (el also becomes 1), so W?la (AL M) is generated.Also, the output of a certain data line becomes "0" continuously. In case,
Similarly, the output of the first multipipe rake 4 becomes "1".

Since the four data lines are monitored together in this way, the circuit can be simplified.

Note that the portion constituted by the inverter 2 and the second AND circuit 3 can also be constituted by, for example, an OR circuit and an inverter that inverts the polarity of its output. Also, the inverter 2 does not need to be concentrated at the input of one of the AND circuits (for example, it may be as shown in FIG. 3. In other words, the high level for the data lines Dt and D3 is
When the low level is "1" and the low level is "0" and the high level is "1" for the data lines D2 and D4, when the output of a certain data line among the data lines DI-Dtt is "0" When the output of the first AND circuit 1 is "0", and when the output of one of the data lines D1 to D is "1", the output of the second AND circuit 3 is "0".
” In this way, various logic circuit configurations are possible.

In addition, the part consisting of the first and second one-shot multi-by-breaks 4 and 5 includes a resistor R and a capacitor C that integrate the input signal, and a reference voltage E , the comparator 12 outputs "1" when the value is lower than . In this case, the time T from when an abnormality occurs to when an alarm is issued is determined by the RC time constant and the reference voltage VRE relative to the power supply voltage.
Determined by the ratio of P.

〔Effect of the invention〕

As described above, according to the present invention, many signal lines can be monitored with a simple circuit, which contributes to miniaturization and cost reduction of the device, and provides great effects.

[Brief explanation of drawings]

FIG. 1 shows an alternative circuit to a professional multi-by-break circuit using a signal monitoring system according to an embodiment of the present invention. In the drawings, 1 and 3 are first and second AND circuits,
2 is impark, 4 and 5 are the first and second one-shot multi-bye break, 6 is logic ka l concave ¥ 2

Claims (1)

[Claims] In a signal monitoring method that monitors whether binary signals of "1" and "0" are normally propagated to multiple signal lines, a state in which "1" is simultaneously output from all the signal lines for a certain period of time is used. As described above, if no detection is made, or if "0" is output simultaneously from all the signal lines for a certain period of time or more,
A signal monitoring method characterized in that if the signal is not detected, it is determined that the signal is abnormal.