JPH01319325A - Clock disconnection monitoring circuit - Google Patents

Abstract

PURPOSE:To eliminate the need for a clock interruption monitor clock signal by devising the circuit such that a counter is reset at each state change of a clock signal, counts other clock signal and the interruption of the clock signal is detected when the counter corresponding to the clock signal reaches a prescribed count. CONSTITUTION:Suppose that the signal state of a clock signal A reaches an L level or an H level consecutively, a counter 2 or 1 counts consecutively the clock signal B without being reset. As a result, since a Qn output of the counter 2 or 1 changes to H, it is recognized that the clock signal A is in the disconnecting state. When the Qn output of any of the counters 1, 2 reaches an H level, it is outputted externally as a clock signal A disconnection detection signal via an OR gate 3, then the disconnecting state of the clock signal A is recognized from the display. Thus, no clock disconnection monitor clock signal is required.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a clock disconnection monitoring circuit in which disconnection of each of a plurality of types of clock signals is detected by other clock signals.

[Conventional technology]

Generally, various types of electronic equipment systems use multiple types of clock signals, and if any of the clock signals becomes disconnected for some reason, the system will go down. Moreover, it is necessary to be detected reliably.

By the way, as a clock interruption monitoring circuit, one disclosed in Japanese Patent Application Laid-open No. 12035/1983 is known. In this case, the disconnection of the clock signal to be monitored is detected by the clock signal for clock disconnection monitoring.

[Problem to be solved by the invention]

However, since a separate clock signal for clock interruption monitoring is required to detect interruption of the clock signal, if the clock signal for clock interruption monitoring itself is interrupted, interruption of the clock signal to be monitored cannot be detected. It turns out.

SUMMARY OF THE INVENTION An object of the present invention is to provide a clock disconnection monitoring circuit that can detect disconnection of each clock signal using other clock signals without requiring a separate clock signal for clock disconnection monitoring when multiple types of clock signals are used. It is to serve.

[Means for Solving Problem 11] The above object is such that a counter is provided corresponding to a clock signal, and this counter is configured to count other clock signals while being reset each time the state of the clock signal changes. achieved.

[For production]

A counter provided for a clock signal is used to detect that the clock signal is continuously at the so-called "H" level or "LI+ level" state (referred to as a stuck fault), and therefore is in an off state. If the clock signal is normal, the counter that is counting other clock signals is reset by the periodic state change of that clock signal, and the count value reaches a predetermined value. However, if the counter is turned off, the reset for the counter will be continuously released and the count value will reach the predetermined value.
With this, disconnection of the clock signal can be detected. When there are two types of clock signals, they will inevitably monitor each other, but when there are three or more types, it is not necessarily necessary to monitor each other between the two types of clock signals. It becomes. For example, assuming that three types of clock signals A, B, and C are used, it is sufficient to monitor A and B, B to monitor C, and CA.

〔Example〕

Hereinafter, the present invention will be explained with reference to the accompanying drawings.

The figure shows a specific configuration of an embodiment of the clock failure monitoring circuit according to the present invention when there are two types of clock signals.

As shown in the figure, counters 1 and 2 are activated in response to clock signal A.
The counter 1 is in the signal state "L re" of the clock signal A, and the counter 2 is in the signal state "H re".
”, but both of these are configured to count the clock signal B. On the other hand, the counter 4 provided corresponding to the clock signal B
, 5 are also the signal states of clock signal B 14 L I
Although they are reset by I and It HII,
Both are configured to count the clock signal A.

Now, in general, the periods and phases of clock signals A and B are different, but considering the difference in period, a constant value (
In this example, Qn output is the first for counters 1 and 2.
This is the count value when it becomes "H'". Similarly, when setting the count value for counters 4 and 5 when the 0m output becomes "HII" for the first time, clock signals A and B are If both are normal, counters 1 and 2
, 4.5 are reset periodically before reaching their constant value. However, for example, if the signal state of clock signal A is continuously in the 11 L level state or "H" level state, counter 2 or counter 1 will continue to count clock signal B without being reset. As a result, the Qn output of counter 2 or counter 1 becomes +
Since it changes to 1 HII, the clock signal A
It is known that the system is in a disconnected state. counter 1,
If the Qn output in either of 2 becomes "H" level,
Since this is output and displayed to the outside as a clock signal A disconnection detection signal via the OR gate 3, it is known from this display that the clock signal A is in the disconnected state. This situation is exactly the same for the clock signal, and if the 0m output from either counter 4 or 5 is 11
When H11 is reached, a clock signal B disconnection detection signal can be obtained from the OR gate 6.

As mentioned above, if there are only two types of clock signals, the clock signals will monitor each other, but if there are three or more types, a counter will be provided for each clock signal, and another appropriate clock signal will be connected to the counter. For example, if there are three types of clock signals A, B, and C, the clock signal A should be input.

The counters corresponding to B and C are reset each time the state of the corresponding clock signal changes, and the counters corresponding to clock signal C
, A, and B, respectively. 2
Assuming that more than one type of clock signal is not interrupted at the same time, the interrupted clock signal can be easily detected by any of the remaining normal or locked signals.

Note that in the above example, two counters are provided corresponding to the clock signal, but if a change in the state of the clock signal is detected and the counter is reset based on this, one counter is provided.
It will end up being just that.

〔Effect of the invention〕

As explained above, according to the present invention, the disconnection of each of the plurality of types of clock signals can be easily detected by any of the other normal or lock signals without requiring a separate clock signal for clock disconnection monitoring. There is.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a specific configuration of an example of a clock interruption monitoring circuit according to the present invention. 1.2, 4.5...counter, 3,6...or gate. Patent author Masami Akimoto (1 other person) Patent attorney representing Hitachi Communication Systems Co., Ltd.

Claims (1)

[Claims] 1. A clock failure monitoring circuit provided corresponding to each of a plurality of types of clock signals, in which a counter provided corresponding to each clock signal is reset each time the state of the clock signal changes, and a counter provided corresponding to each clock signal is reset every time the state of the clock signal changes. 1. A clock disconnection monitoring circuit configured to count clock signals of the clock signal and detect the clock signal as disconnected when a counter corresponding to the clock signal reaches a predetermined count value.