JPS62109150A - Bus control circuit - Google Patents

Abstract

PURPOSE:To halve the maximum sum total of variation components of electric current flowing to bus signal lines by inverting and outputting the logic state of signals when the combination of the logic states of signal line groups satisfies prescribed conditions. CONSTITUTION:A majority decision circuit 1 decides the logic states of N pieces of signals X1-XN to be led to a bus. Then '0' and '1' are outputted as a control signal C if the number of '0' is less than N/2 and larger than N/2+1 among those signals X1-XN. These signals X1-XN are inverted by an EX-OR gate 2 only when the signal C is set at '1' and turned into signals Y1-YN to be sent to a bus together with the signal C. At the receiver side, the received signals Y2-YN are inverted by an EX-OR gate 3 only when the signal C is equal to '1'. Thus signals Z1-ZN are obtained. Thus the number of signal lines which are equal to '0' is set at N/2 at the maximum among those signals Y1-YN.

Description

[Detailed description of the invention] 3. tl of the invention [Industrial application field] The present invention relates to a bus consisting of a plurality of signal line groups for transmitting digital signals, such as a computer address bus or a data bus. In particular, the present invention relates to a circuit that controls the logic state of a signal sent to a bus.

[Conventional technology]

The logic state of all signal lines that make up the bus is “0” at the same time
When changing from “1” to “1” or from “1” to “0”,
The sum of the changes in the currents flowing through all the 1d lines is the maximum, and it is necessary to flow a current of the same magnitude and in the opposite direction on the ground line of the bus. For this reason, conventional buses needed to have approximately the same number of ground lines as signal lines.

[Problem that the invention seeks to solve]

Therefore, as the capacity of the bus becomes larger (addition of PL to the signal 'IMm), the number of ground lines must also increase, and there is a drawback that the total number of lines on the bus becomes enormous. Furthermore, since the sum total of changes in the current flowing through the ground line becomes enormous, there is a drawback that it may cause malfunction of the circuit.

[Failure to solve the problem]

In order to solve the above-mentioned drawbacks, the bus control circuit of the present invention monitors the logical state of the output signal on the output side of the bus, and as a result of the monitoring, when the combination of the logical states of each signal line group reaches a certain condition, the signal The logic state of the signal is inverted and output.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows an example of a transmission side circuit of a bus control circuit according to the present invention.

In the figure, N signals X1 to be sent to the bus
The logic state of XN is determined by the majority decision circuit 1, and the signal
If the number of "0"s among ~XN is less than or equal to N/2, "0" is outputted, and if it is greater than or equal to N/2+1, "1" is outputted as the control signal C. Signals X1 to XN are EX only when signal C is “1”
-OR gate 2 inverts the signals Y1 to YN, which are sent out together with signal C to the node.

Figure 2 shows the receiving side of the bus, where the received signal Y2
~YN is inverted by EX-OR gate 3 only when signal C is 1 to obtain signals Z1~ZN. As a result, the signal Z1~
ZN has the same logical state as X1 to XN, respectively.

As a result of the above, the number of signal lines that become "0" among the signals Y1 to YN on the bus is at most N/2, and the maximum value of the sum of the changes in current due to changes in the logic state of the signals Y1 to YN is the signal X
This is 1/2 of the case where 1-XN is sent to a single-connection bus.

〔Effect of the invention〕

As explained above, according to the present invention, the maximum value of the sum of the changes in the current flowing in the signal line of the bus can be reduced to 1/2, and as a result, the maximum value of the sum of the changes in the current flowing in the ground line Since the number of ground wires is also 1/2, the number of ground wires is also 1/2.
This has the effect of reducing the cause of circuit malfunction f'μ caused by the current flowing through the ground line. In addition, the circuit configuration is extremely simple and the time delay due to one circuit is small, so there is almost no deterioration in bus performance.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a receiving side circuit diagram for the circuit shown in FIG. l...Majority decision circuit, 2.3...-E
X-OR gate.

Claims (1)

[Claims] In a bus consisting of multiple signal line groups that transmit digital signals of "0" or "1," the logic state of the output signal is monitored on the signal output side, and as a result of the monitoring, the combination of the logic states of each signal line group is determined. A bus control circuit characterized in that when a certain predetermined condition is met, the logic state of some or all of the signal lines is inverted and output.