JPS6156474A - Manufacture of gallium nitride semiconductor device - Google Patents

Manufacture of gallium nitride semiconductor device

Info

Publication number
JPS6156474A
JPS6156474A JP59179709A JP17970984A JPS6156474A JP S6156474 A JPS6156474 A JP S6156474A JP 59179709 A JP59179709 A JP 59179709A JP 17970984 A JP17970984 A JP 17970984A JP S6156474 A JPS6156474 A JP S6156474A
Authority
JP
Japan
Prior art keywords
layer
gan layer
gallium nitride
gan
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59179709A
Other languages
Japanese (ja)
Inventor
Toshiharu Kawabata
川端 敏治
Susumu Furuike
進 古池
Toshio Matsuda
俊夫 松田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP59179709A priority Critical patent/JPS6156474A/en
Publication of JPS6156474A publication Critical patent/JPS6156474A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26Materials of the light emitting region
    • H01L33/30Materials of the light emitting region containing only elements of group III and group V of the periodic system
    • H01L33/32Materials of the light emitting region containing only elements of group III and group V of the periodic system containing nitrogen
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/0004Devices characterised by their operation
    • H01L33/0008Devices characterised by their operation having p-n or hi-lo junctions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48464Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/49105Connecting at different heights
    • H01L2224/49109Connecting at different heights outside the semiconductor or solid-state body

Abstract

PURPOSE:To enable the formation of electrodes to the lower GaN layer by forming an apertuer in the surface GaN layer by a method wherein two or more of GaN layers are formed on a substrate, and a protection film is formed on the surface; next, an aperture is formed in the protection film, and heat treatment is carried out in a gas atmosphere containing hydrogen chloride gas. CONSTITUTION:An N type GaN layer 2 and a P type GaN layer 3 of insulation or high resistivity are formed on a sapphire substrate 1, and an Si dioxide film 10 is deposited on the GaN layer 3 of the outermost surface. Using this Si dioxide film 10 as the protection mask member, after an aperture is selectively provided thereto, heat treatment is carried out at 500 deg.C with flows of the mixed gas of AR and HCl, when the GaN layer 3 of the outermost surface exposed to this aperture is removed; accordingly, the lower GaN layer 2 is exposed. Next, the Si dioxide film 10 the protection film is removed; thereafter, an Al film is formed by evaporation and patterned into the first electrode layer 4 and the second electrode layer 11.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、窒化ガリウム(以下、G a Nと記す)半
導体装置の製造方法、詳しくは、同G a Nへの電極
形成方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for manufacturing a gallium nitride (hereinafter referred to as GaN) semiconductor device, and more particularly to a method for forming electrodes on GaN.

従来例の構成とその問題点 GaNは、青色発光素子の半導体材料として有望視され
ているが、大きな単結晶がなかなか実現できず、通常、
電気的に絶縁性のサファイア基板上に気相法でエピタキ
シャル成長させたものが用いられる。
Conventional configurations and their problems Although GaN is seen as a promising semiconductor material for blue light-emitting devices, large single crystals are difficult to realize, and usually
It is epitaxially grown on an electrically insulating sapphire substrate using a vapor phase method.

G a Nはイオン結合性の強い結晶で、シリコン(S
t)や砒化ガリウム(GaAs )などの共有結晶に比
較して、結晶が不完全で、窒素(N)の空孔などの結晶
欠陥を多く含んでいる。また、このG a N結晶では
、窒素の空孔はドナーとして振舞うので、不純物を添加
しなくても、低抵抗のn型半導体となることが多い。そ
こで、アクセプタ不純物を添加しても、そのほとんどが
電荷補償で費やされ、せいぜい絶縁体になるか、あるい
は高抵抗のp型(π型ともいう)の半導体になる程度で
、なかなか低抵抗のp型半導体が得られない。このため
、G a Nの青色発光素子は、完全なpm接合ではな
く、概ね、i(π)n接合構造であることが多い。第1
図は、従来のG a N発光素子の概略断面図であシ、
サファイア基板1上のn型G a N層2に、亜鉛(Z
n)を添加した高比抵抗性のi(π)型G a N層3
を厚さ1μm程度に形成したもので、このi(π)型G
 a N層3上には金属の電極層4を設けて、それに金
属細線5を圧着する。
GaN is a crystal with strong ionic bonding properties, and is a crystal with strong ionic bonding properties.
Compared to covalent crystals such as t) and gallium arsenide (GaAs), the crystal is incomplete and contains many crystal defects such as nitrogen (N) vacancies. Furthermore, in this GaN crystal, nitrogen vacancies act as donors, so it often becomes a low-resistance n-type semiconductor even without adding impurities. Therefore, even if an acceptor impurity is added, most of it will be spent on charge compensation, and at most it will become an insulator or a high-resistance p-type (also called π-type) semiconductor. A p-type semiconductor cannot be obtained. For this reason, GaN blue light emitting elements often have an i(π)n junction structure rather than a perfect pm junction structure. 1st
The figure is a schematic cross-sectional view of a conventional GaN light emitting device.
Zinc (Z) is added to n-type GaN layer 2 on sapphire substrate 1.
High resistivity i(π) type GaN layer 3 added with n)
is formed to a thickness of about 1 μm, and this i(π) type G
a A metal electrode layer 4 is provided on the N layer 3, and a thin metal wire 5 is crimped onto it.

ところが、n型G a N層2への電極形成は、なかな
か面倒である。すなわち、G a N結晶は化学的に安
定性の高い物質で、薬品による化学的なエツチングが困
難であるため、通常は、第1図示のように、n型G a
 N層2の側面にインジウム電極部6を設け、他方の電
極部7との間を針状細線8により、金属ステム9に電気
的に接続する方策が用いられる。しかし、n型G a 
N層2の厚さもせいぜい20〜30μmの厚さしかなく
、インジウム電極部6の形成ならびにこの部位への針状
細線8の接続作業は至難であシ、製造性の悪いものであ
った。
However, forming electrodes on the n-type GaN layer 2 is quite troublesome. In other words, GaN crystal is a highly chemically stable substance and is difficult to chemically etch using chemicals.
A method is used in which an indium electrode part 6 is provided on the side surface of the N layer 2 and the other electrode part 7 is electrically connected to the metal stem 9 by a thin needle wire 8. However, n-type Ga
The thickness of the N layer 2 was only 20 to 30 μm at most, and it was extremely difficult to form the indium electrode portion 6 and to connect the thin needle wire 8 to this portion, resulting in poor productivity.

発明の目的 本発明は、G a N層を選択的に除去することができ
る技術を開発し、これでもって、表面のGaN層に開口
を形成して、これを通じて、下層のG a N層に電極
形成可能な製造方法を提供するものである。
OBJECTS OF THE INVENTION The present invention has developed a technique that can selectively remove the GaN layer, thereby forming an opening in the surface GaN layer, through which the underlying GaN layer is exposed. The present invention provides a manufacturing method capable of forming electrodes.

発明の構成 本発明は、要約するに、基板上に少なくとも2層のG 
a N層を形成したのち、前記構造の最表面層の表面に
保護被膜を形成し、ついで、前記保護被膜を選択的に除
去して、開口部を形成し、塩化水素ガスを含む気体雰囲
気中での熱処理により、前記開口部に露出した前記最表
面層のG a N層を除去し、同開口部に露出した前記
最表面層下のG a N層に電極を形成する工程をそな
えたものであシ、これにより最表面およびその直下のG
 a N層のそれぞれの表面に対して平坦な電極層を形
成することができるので、G a Nの半導体装置が通
     1常のワイヤポンド技術で組立て可能となり
、GaN半導体装置の製造性が大幅に向上する。
Structure of the Invention In summary, the present invention provides at least two layers of G on a substrate.
a After forming the N layer, a protective film is formed on the surface of the outermost layer of the structure, and then the protective film is selectively removed to form an opening, and the film is exposed to a gas atmosphere containing hydrogen chloride gas. The step of removing the GaN layer of the outermost surface layer exposed to the opening through heat treatment and forming an electrode on the GaN layer below the outermost surface layer exposed to the opening. As a result, the uppermost surface and the G immediately below it
Since a flat electrode layer can be formed on each surface of the aN layer, GaN semiconductor devices can be assembled using normal wire bonding technology, greatly improving the manufacturability of GaN semiconductor devices. improves.

実施例の説明 つぎに、本発明を実施例によシ、詳しく説明する。Description of examples Next, the present invention will be explained in detail using examples.

第2図a −Cは、本発明実施例の工程順断面図であり
、サファイア基板1上に厚さ約30μmのn型G a 
N層2および厚さ1μm程度の絶縁性ないしは高比抵抗
性p型GaN層3を有する半導体装置の製造過程である
2A to 2C are cross-sectional views in the order of steps of the embodiment of the present invention, in which an n-type Ga with a thickness of about 30 μm is formed on a sapphire substrate 1.
This is a manufacturing process of a semiconductor device having an N layer 2 and an insulating or high resistivity p-type GaN layer 3 with a thickness of about 1 μm.

まず、第2図aのように、最表面のGaN層3上に二酸
化ケイ素膜10を付着させる。そして、この二酸化ケイ
素膜1oを保護マスク材として用い、これに開口部を選
択的に設けたのち、これをアルゴン(Ar)と塩化水素
(HCl )ガスの混合比が2=1の混合ガスを1分間
当り1.51の流量で流しなから5oo℃、20分間の
熱処理を行うと、この開口部に露出した最表面のG a
 N層3が除去されて、第2図すのように、下層のG 
a N層2が露出される。なお、この熱処理において、
熱処理温度がaOO℃の場合に約8μm、同じく、60
0℃の場合に約4μm、同じく、500℃の場合に約2
μmのGaN層が除去されるが、最表面のG a N層
3の厚さはせいぜい1μmであり、したがって、これを
こえるような条件下で熱処理を実施すると、最表面のG
 a N層3が確実に分解除去され、下層のGaN層2
の表面が現れる。
First, as shown in FIG. 2a, a silicon dioxide film 10 is deposited on the outermost GaN layer 3. Then, this silicon dioxide film 1o is used as a protective mask material, and after selectively providing openings in it, it is filled with a mixed gas of argon (Ar) and hydrogen chloride (HCl) gas with a mixing ratio of 2=1. When heat treatment is performed at 50°C for 20 minutes while flowing at a flow rate of 1.51 per minute, the Ga of the outermost surface exposed in this opening is
The N layer 3 is removed and the underlying G layer is removed as shown in Figure 2.
a N layer 2 is exposed. In addition, in this heat treatment,
When the heat treatment temperature is aOO℃, it is about 8 μm, and similarly, it is 60 μm.
Approximately 4 μm at 0°C, and approximately 2 μm at 500°C
The thickness of the GaN layer 3 on the outermost surface is at most 1 μm, so if heat treatment is performed under conditions exceeding this, the thickness of the GaN layer 3 on the outermost surface will be removed.
a The N layer 3 is reliably decomposed and removed, and the underlying GaN layer 2
surface appears.

次に、保護被膜の二酸化ケイ素膜10を除去したのち、
アルミニウムCAl )膜を蒸着形成し、これにパター
ンニングを行い、第2図Cのように、第1の電極層4お
よび第2の電極層11を形成する。
Next, after removing the silicon dioxide film 10 as a protective coating,
An aluminum (CAl) film is deposited and patterned to form a first electrode layer 4 and a second electrode layer 11 as shown in FIG. 2C.

第3図は、金属ステム9上に、第2図Cで示す実施例の
半導体装置を組み込んだものの概略断面図であり、金属
細線5を用いて、通常のワイヤボンディング技術で電極
接続を行なったものである。
FIG. 3 is a schematic cross-sectional view of the semiconductor device of the embodiment shown in FIG. 2C installed on a metal stem 9. Electrode connections were made using a thin metal wire 5 by ordinary wire bonding technology. It is something.

発明の効果 本発明によれば、保護被膜に二酸化ケイ素を用いて、こ
れをマスクに、開口部を通じて、露出面のG a N層
を塩化水素ガスを含む気体雰囲気中で熱処理することに
よシ、G a N層の選択的除去が行われ、この技術を
用いることにより、G a N結晶を用いる半導体装置
で、平面的電極部の形成が可能になり、製造性が格段に
向上する。
Effects of the Invention According to the present invention, silicon dioxide is used as a protective film, and silicon dioxide is used as a mask to heat-treat the exposed surface of the GaN layer through the opening in a gas atmosphere containing hydrogen chloride gas. , selective removal of the GaN layer is performed, and by using this technique, it becomes possible to form a planar electrode portion in a semiconductor device using GaN crystal, and the manufacturability is significantly improved.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来例のGaN発光素子の概略断面図、第2図
a −Cは本発明実施例の工程順断面図、第3図は本発
明の実施例で得られたG a N発光素子の概略断面図
である。 1・・・・・・サファイア基板、2・・・・・・n型G
 a N層、3・・・・・・i(π)型G a N層、
4,11・・・・・・電極層、5・・・・・・金属細線
(ボンディングワイヤ)。 代理人の氏名 弁理士 中 尾 敏 男 ほか1名第1
図 ○        ■ 第2図 第3図
FIG. 1 is a schematic sectional view of a conventional GaN light emitting device, FIG. 2 a-C is a step-by-step sectional view of an example of the present invention, and FIG. 3 is a GaN light emitting device obtained in an example of the present invention. FIG. 1... Sapphire substrate, 2... N-type G
a N layer, 3...i (π) type Ga N layer,
4, 11...electrode layer, 5...metal thin wire (bonding wire). Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure ○ ■ Figure 2 Figure 3

Claims (2)

【特許請求の範囲】[Claims] (1)基板上に少なくとも2層の窒化ガリウム層を形成
した後、最表面層の前記窒化ガリウム層表面に保護被膜
を形成し、ついで、前記保護被膜を選択的に除去して、
開口部を形成し、塩化水素ガスを含む気体雰囲気中での
熱処理により、前記開口部に露出した最表面層の前記窒
化ガリウム層を除去し、同開口部に露出した最表面層下
の前記窒化ガリウム層に電極を形成する工程をそなえた
窒化ガリウム半導体装置の製造方法。
(1) After forming at least two gallium nitride layers on the substrate, forming a protective film on the surface of the gallium nitride layer, which is the outermost layer, and then selectively removing the protective film,
An opening is formed, and the gallium nitride layer of the outermost surface layer exposed to the opening is removed by heat treatment in a gas atmosphere containing hydrogen chloride gas, and the nitride layer below the outermost surface layer exposed to the opening is removed. A method for manufacturing a gallium nitride semiconductor device, which includes a step of forming an electrode on a gallium layer.
(2)最表面の窒化ガリウム層が絶縁性もしくは下層の
窒化ガリウム層と反対導電性でなる特許請求の範囲第1
項記載の窒化ガリウム半導体装置の製造方法。
(2) Claim 1 in which the outermost gallium nitride layer is insulating or has a conductivity opposite to that of the underlying gallium nitride layer.
A method for manufacturing a gallium nitride semiconductor device as described in 1.
JP59179709A 1984-08-28 1984-08-28 Manufacture of gallium nitride semiconductor device Pending JPS6156474A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59179709A JPS6156474A (en) 1984-08-28 1984-08-28 Manufacture of gallium nitride semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59179709A JPS6156474A (en) 1984-08-28 1984-08-28 Manufacture of gallium nitride semiconductor device

Publications (1)

Publication Number Publication Date
JPS6156474A true JPS6156474A (en) 1986-03-22

Family

ID=16070500

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59179709A Pending JPS6156474A (en) 1984-08-28 1984-08-28 Manufacture of gallium nitride semiconductor device

Country Status (1)

Country Link
JP (1) JPS6156474A (en)

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01278026A (en) * 1988-04-29 1989-11-08 Toyoda Gosei Co Ltd Semiconductor dry etching method
JPH01278025A (en) * 1988-04-29 1989-11-08 Toyoda Gosei Co Ltd Semiconductor dry-etching method
JPH03252174A (en) * 1990-02-28 1991-11-11 Toyoda Gosei Co Ltd Surface processing of gallium nitride compound semiconductor
JPH05129658A (en) * 1991-10-30 1993-05-25 Toyoda Gosei Co Ltd Gallium nitride compound semiconductor light emission device
JPH05183189A (en) 1991-11-08 1993-07-23 Nichia Chem Ind Ltd Manufacture of p-type gallium nitride based compound semiconductor
JPH08316529A (en) * 1996-05-16 1996-11-29 Toyoda Gosei Co Ltd Gallium nitride compound semiconductor light emitting device
EP0762486A2 (en) * 1995-07-29 1997-03-12 Hewlett-Packard Company Etching of nitride crystal
JPH09129924A (en) * 1995-10-27 1997-05-16 Toyoda Gosei Co Ltd Iii group nitride semiconductor etching method and light emitting element manufacturing method
JP2003110139A (en) * 2001-09-28 2003-04-11 Sanyo Electric Co Ltd Nitride semiconductor light emitting element
US6734091B2 (en) 2002-06-28 2004-05-11 Kopin Corporation Electrode for p-type gallium nitride-based semiconductors
US6847052B2 (en) 2002-06-17 2005-01-25 Kopin Corporation Light-emitting diode device geometry
US6881983B2 (en) 2002-02-25 2005-04-19 Kopin Corporation Efficient light emitting diodes and lasers
JP2008530778A (en) * 2005-02-04 2008-08-07 ソウル オプト デバイス カンパニー リミテッド Light emitting device having a plurality of light emitting cells and method for manufacturing the same
JP2013093542A (en) * 2011-10-24 2013-05-16 Lg Innotek Co Ltd Light emitting device

Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01278025A (en) * 1988-04-29 1989-11-08 Toyoda Gosei Co Ltd Semiconductor dry-etching method
JPH01278026A (en) * 1988-04-29 1989-11-08 Toyoda Gosei Co Ltd Semiconductor dry etching method
JPH03252174A (en) * 1990-02-28 1991-11-11 Toyoda Gosei Co Ltd Surface processing of gallium nitride compound semiconductor
JP2666228B2 (en) * 1991-10-30 1997-10-22 豊田合成株式会社 Gallium nitride based compound semiconductor light emitting device
JPH05129658A (en) * 1991-10-30 1993-05-25 Toyoda Gosei Co Ltd Gallium nitride compound semiconductor light emission device
JPH05183189A (en) 1991-11-08 1993-07-23 Nichia Chem Ind Ltd Manufacture of p-type gallium nitride based compound semiconductor
EP0762486A2 (en) * 1995-07-29 1997-03-12 Hewlett-Packard Company Etching of nitride crystal
EP0762486A3 (en) * 1995-07-29 1997-12-29 Hewlett-Packard Company Etching of nitride crystal
US5814239A (en) * 1995-07-29 1998-09-29 Hewlett-Packard Company Gas-phase etching and regrowth method for Group III-nitride crystals
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