JPH02263478A - Manufacture of semiconductor element - Google Patents
Manufacture of semiconductor elementInfo
- Publication number
- JPH02263478A JPH02263478A JP1085560A JP8556089A JPH02263478A JP H02263478 A JPH02263478 A JP H02263478A JP 1085560 A JP1085560 A JP 1085560A JP 8556089 A JP8556089 A JP 8556089A JP H02263478 A JPH02263478 A JP H02263478A
- Authority
- JP
- Japan
- Prior art keywords
- film
- gaas
- semiconductor
- films
- cracks
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 39
- 238000004519 manufacturing process Methods 0.000 title claims description 21
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 239000013078 crystal Substances 0.000 claims abstract description 6
- 238000010438 heat treatment Methods 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 14
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 27
- 230000002159 abnormal effect Effects 0.000 abstract description 4
- 238000006243 chemical reaction Methods 0.000 description 11
- 238000005530 etching Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、光電変換素子等に利用される半導体素子の製
造方法に関し、特にSi等の半導体基板上に導電型が異
なった複数層の化合物半導体膜をエピタキシャル成長さ
せる半導体素子の製造方法に関するものである。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor element used in a photoelectric conversion element, etc., and particularly relates to a method for manufacturing a semiconductor element used in a photoelectric conversion element, etc. The present invention relates to a method of manufacturing a semiconductor element by epitaxially growing a semiconductor film.
GaAs等の化合物半導体は、高効率な光電変換素子等
の半導体素子の材料として多く用いられている。その製
造方法としては、素子の低コスト化の観点から、これら
の化合物半導体をSi基板等の半導体基板上にエピタキ
シャル成長させることが一般的である。以下、叶n接合
を有する光電変換素子を例として、従来の半導体素子の
製造方法について簡単に説明する。Compound semiconductors such as GaAs are often used as materials for semiconductor elements such as highly efficient photoelectric conversion elements. As a manufacturing method thereof, from the viewpoint of reducing the cost of the device, it is common to epitaxially grow these compound semiconductors on a semiconductor substrate such as a Si substrate. Hereinafter, a conventional method for manufacturing a semiconductor device will be briefly described using a photoelectric conversion device having an n-junction as an example.
第3図はこの従来の製造方法の工程を示す模式的断面図
である。まずn−Si基板11上に、厚さ200人程定
形非晶質なGaAs層を含むSeドープしたn−GaA
sJl!12. Znドープしたp−GaAs膜13膜
上3順に、MOCVD(Metalorganic C
hemical Vapor Depositton
)法にてエピタキシャル成長させる(第3図(a))。FIG. 3 is a schematic cross-sectional view showing the steps of this conventional manufacturing method. First, on the n-Si substrate 11, a Se-doped n-GaA layer containing a regular amorphous GaAs layer with a thickness of approximately 200 mm is prepared.
sJl! 12. MOCVD (Metalorganic Carbon
Chemical Vapor Depositton
) method (FIG. 3(a)).
次に、p−GaAs膜13膜上3にAu/Zn膜14を
パターン形成すると共に、n−5i基板11の下面にA
I膜15を蒸着し、450°C程度の熱処理を施してオ
ーミック電極を形成する(第3図(b))。最後に、p
−n接合ダイオード端面に流れるリーク電流を小さくす
るために、n−GaAs膜12及びp−GaAs膜13
からなる半導体膜の端面をエツチング処理して、光電変
換素子を製造する(第3図(C))。Next, an Au/Zn film 14 is patterned on the p-GaAs film 13, and an A/Zn film 14 is formed on the lower surface of the n-5i substrate 11.
An I film 15 is deposited and heat treated at about 450°C to form an ohmic electrode (FIG. 3(b)). Finally, p
- In order to reduce the leakage current flowing to the end face of the n-junction diode, the n-GaAs film 12 and the p-GaAs film 13 are
A photoelectric conversion element is manufactured by etching the end face of the semiconductor film (FIG. 3(C)).
〔発明が解決しようとする課題]
上述したような方法にて製造される光電変換素子の中に
は、異常に大きなリーク電流が発生する素子が数多く存
在し、製造の歩留りが著しく低いという問題があった。[Problems to be Solved by the Invention] Among the photoelectric conversion elements manufactured by the method described above, there are many elements that generate an abnormally large leakage current, and there is a problem that the manufacturing yield is extremely low. there were.
そしてこのリーク電流が発生する原因は、SiとGaA
sとの熱膨脹係数の差によってGaAs膜に生じたクラ
ックにAu/Znが異常に拡散し、Au/Zn膜14と
n−GaAs膜12とが短絡するからであることを、本
発明者は実験的に立証した。またこのクラックが生じる
方向の大部分は、n−5i基板11の特定の結晶方向と
これに垂直な方向とであることが判った。The cause of this leakage current is Si and GaA.
The present inventor has experimentally determined that this is because Au/Zn abnormally diffuses into cracks that occur in the GaAs film due to the difference in thermal expansion coefficient between the Au/Zn film 14 and the n-GaAs film 12. It was proved. It was also found that most of the directions in which these cracks occur are in a specific crystal direction of the n-5i substrate 11 and in a direction perpendicular to this.
本発明はかかる事情に鑑みてなされたものであり、クラ
ックが生じ易い方向に半導体膜の不完全結晶領域を形成
して、熱処理して合金化される電極の下部の半導体膜に
はクラックを生じさせないようにすることにより、リー
ク電流の発生を防止し、製造の歩留りを向上することが
できる半導体素子の製造方法を提供することを目的とす
る。The present invention has been made in view of the above circumstances, and it is possible to form an imperfectly crystalline region of a semiconductor film in a direction in which cracks are likely to occur, thereby causing cracks in the semiconductor film under the electrode that is heat-treated and alloyed. It is an object of the present invention to provide a method for manufacturing a semiconductor device that can prevent leakage current from occurring and improve manufacturing yield by preventing leakage current from occurring.
本発明に係る半導体素子の製造方法は、半導体基板上に
、導電型が異なった複数層の半導体膜をエピタキシャル
成長させる半導体素子の製造方法において、前記半導体
基板上に、前記半導体基板の特定の結晶方向とその垂直
方向とにわたって格子状に、前記半導体膜の不完全結晶
領域を形成する工程と、前記不完全結晶領域を除く各領
域に電極を形成して熱処理を施す工程と、形成した各電
極を導電性膜にて結線する工程とを有することを特徴と
する。A method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device in which a plurality of layers of semiconductor films having different conductivity types are epitaxially grown on a semiconductor substrate. a step of forming imperfectly crystalline regions of the semiconductor film in a lattice shape in the vertical direction thereof; a step of forming electrodes in each region except the imperfectly crystalline regions and subjecting them to heat treatment; The method is characterized by comprising a step of connecting wires using a conductive film.
本発明の製造方法にあっては、クラックが生じ易い半導
体基板の特定方向及びそれに垂直な方向にわたって格子
状に半導体膜の不完全結晶領域を形成する。そうしてお
くと、室温まで温度を下降させた際に、クラックはこの
不完全結晶領域においてのみ集中的に生じ、電極を形成
する領域ではクラックは生じない。従って電極を構成す
る材料の半導体膜への従来のような異常拡散は防止され
、リーク電流は発生しない。In the manufacturing method of the present invention, imperfectly crystalline regions of a semiconductor film are formed in a lattice pattern over a specific direction of a semiconductor substrate where cracks are likely to occur and in a direction perpendicular thereto. If this is done, when the temperature is lowered to room temperature, cracks will occur intensively only in this imperfect crystal region, and no cracks will occur in the region where the electrodes will be formed. Therefore, the conventional abnormal diffusion of the material constituting the electrode into the semiconductor film is prevented, and no leakage current occurs.
以下、本発明をその実施例を示す図面に基づいて具体的
に説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below based on drawings showing embodiments thereof.
第1図は本発明の製造方法の工程を示す模式的断面図、
第2図は同じくその上面図である。本実施例では、方形
のn−Si基板上を3×3の光電変換部に分割した構成
をなす光電変換素子を例として、その半導体素子の製造
方法を説明する。FIG. 1 is a schematic cross-sectional view showing the steps of the manufacturing method of the present invention,
FIG. 2 is also a top view thereof. In this embodiment, a method for manufacturing a semiconductor device will be described using as an example a photoelectric conversion element having a structure in which a rectangular n-Si substrate is divided into 3×3 photoelectric conversion sections.
まず(100)面から[011]方向に2°傾いた半導
体基板たるn−Si基板1上に、光電変換部を100μ
m間隔に分割するように、100μm間隔にて幅10μ
m程度のSiN膜6を厚さ2000人程度1格子状にパ
ターン形成する(第1図(a))。このSiN膜6は、
[011]方向とこれと垂直な方向とに帯状に形成する
こととし、SiN膜6は第2図(a)に示すような格子
状パターンをなす。またこの工程におけるバターニング
は、通常のフォトリソグラフィとエツチングとを用いる
。First, a photoelectric conversion unit with a thickness of 100 μm is placed on an n-Si substrate 1, which is a semiconductor substrate, tilted 2 degrees in the [011] direction from the (100) plane.
The width is 10μ at 100μm intervals so that it is divided into m intervals.
A SiN film 6 having a thickness of approximately 2,000 m is patterned into a lattice shape (FIG. 1(a)). This SiN film 6 is
The SiN film 6 is formed in a strip shape in the [011] direction and in a direction perpendicular thereto, and the SiN film 6 forms a lattice pattern as shown in FIG. 2(a). Further, the patterning in this step uses ordinary photolithography and etching.
次にMOCVD法を用いて、450°Cにて低温成長さ
せる厚さ200Å以下の非晶質なGaAs層を含んだ厚
さ3um程度のn−GaAs膜2.及びp−GaAs膜
3を、SiN膜6の表面を含んでn−5i基板1上にこ
の順に約700℃の成長温度でエピタキシャル成長させ
る(第1図(b))。半導体膜を成長させた後、室温ま
で温度を下降させると、StとGaAsとの熱膨脹係数
の違いによって、GaAs膜に応力が加えられる。とこ
ろが本発明では、SiN膜6の上部におけるGaAs膜
は完全には結晶化せずに多結晶または非晶質状である、
つまりこの部分(SiN膜6の上部におけるGaAs膜
)は不完全結晶領域であるので、この部分のみに第1図
(b)に示す如く集中的にクラックCが生じることにな
り、他の部分にはクランクは生じない。Next, an n-GaAs film with a thickness of about 3 um including an amorphous GaAs layer with a thickness of 200 Å or less is grown at a low temperature of 450° C. using the MOCVD method. A p-GaAs film 3 and a p-GaAs film 3 are epitaxially grown in this order on the n-5i substrate 1 including the surface of the SiN film 6 at a growth temperature of about 700°C (FIG. 1(b)). After growing a semiconductor film, when the temperature is lowered to room temperature, stress is applied to the GaAs film due to the difference in thermal expansion coefficients between St and GaAs. However, in the present invention, the GaAs film above the SiN film 6 is not completely crystallized and is polycrystalline or amorphous.
In other words, since this part (the GaAs film on top of the SiN film 6) is an imperfect crystal region, cracks C occur intensively only in this part as shown in FIG. 1(b), and in other parts. No crank occurs.
次いで、フォトリソグラフィを用いたリフトオフ法によ
り、各光電変換部のp−GaAs膜3上膜厚上5000
人程度0Au/Zn(Zn含有率5%)膜4を形成する
と共に、n−5t基板1の下面にAl膜5を蒸着する(
第1図(C)、第2図(b))。次に450°Cにて2
分間にわたって加熱処理を施して、p−GaAs膜3と
Au/Zn膜4との合金化及びn−Si基板1とAI膜
5との合金化をはかる。この際Au/Zn膜4の下部で
はクラックは生じていないので、異常なリーク電流の原
因となるAu/Znのp−GaAs膜3を経てn−Ga
As膜2まで達する異常拡散は起こらない。Next, by a lift-off method using photolithography, the thickness of the p-GaAs film 3 of each photoelectric conversion section is 5000 mm.
A 0 Au/Zn (Zn content: 5%) film 4 is formed, and an Al film 5 is vapor-deposited on the lower surface of the n-5t substrate 1 (
Fig. 1(C), Fig. 2(b)). Then at 450°C 2
Heat treatment is performed for a minute to alloy the p-GaAs film 3 and the Au/Zn film 4 and to alloy the n-Si substrate 1 and the AI film 5. At this time, since no cracks have occurred in the lower part of the Au/Zn film 4, the n-Ga
Abnormal diffusion reaching the As film 2 does not occur.
次に、不完全結晶領域におけるp−n接合間のリーク電
流及びp−n接合端面におけるリーク電流をなくすため
に、不完全結晶領域であるGaAs膜部分を、11□S
04.H20□、!1□0の混合溶液にてフォトリソグ
ラフィを用いてエツチング除去する(第1図(d))。Next, in order to eliminate the leakage current between the p-n junction in the imperfectly crystalline region and the leakage current at the end face of the pn junction, the GaAs film portion, which is the imperfectly crystalline region, was
04. H20□,! Etching is performed using photolithography using a mixed solution of 1□0 (FIG. 1(d)).
最後に光透過性を有する耐熱ガラス7の表面にリフトオ
フ法により選択的に形成された厚さ1μm程度の導電性
膜たるAu膜8を各電極(Au/Zn膜4)に貼合せる
ことにより、各電極を結線して光電変換素子を製造する
(第1図(e)、第2図(C))。ここで耐熱ガラス7
は、素子を保護する働きがある。Finally, an Au film 8, which is a conductive film with a thickness of about 1 μm, is selectively formed on the surface of the heat-resistant glass 7 having light transmittance by a lift-off method, and is bonded to each electrode (Au/Zn film 4). A photoelectric conversion element is manufactured by connecting each electrode (FIG. 1(e), FIG. 2(C)). Here, heat-resistant glass 7
has the function of protecting the element.
なお本実施例では、エツチングにて不完全結晶領域を除
去することとしたが、この領域が高抵抗である場合には
、エツチングを行わずに、n−GaAs膜2上にリフト
オフ法にて直接厚さ2000人程度0^U膜を蒸着して
各電極を結線することとしてもよい。In this example, the incomplete crystalline region was removed by etching, but if this region has high resistance, it is etched directly onto the n-GaAs film 2 by a lift-off method without etching. A 0^U film having a thickness of about 2000 layers may be deposited to connect each electrode.
(発明の効果]
以上詳述した如く本発明の製造方法では、半導体膜の不
完全結晶領域に選択的にクランクを生じさせて、電極の
下部の半導体膜にはクランクを生じさせないようにした
ので、製造した半導体素子における異常なリーク電流の
発生を防止することができる。この結果、製造の歩留り
を大幅に向上できる等、本発明は優れた効果を奏する。(Effects of the Invention) As detailed above, in the manufacturing method of the present invention, cranks are selectively generated in the imperfectly crystalline regions of the semiconductor film, and cranks are not generated in the semiconductor film below the electrode. The present invention has excellent effects, such as being able to prevent the occurrence of abnormal leakage current in the manufactured semiconductor element.As a result, the manufacturing yield can be significantly improved.
第1図は本発明に係る製造方法の工程を示す模式的断面
図、第2図は同じくその上面図、第3図は従来の製造方
法の工程を示す模式的断面図である。
1 ・・・n−5i基板 2−n−GaAs膜 3−p
−GaAs膜4−−・Au/Zn膜 5・AI膜 5
=SiN膜7・・・耐熱ガラス 8・・・Au膜FIG. 1 is a schematic cross-sectional view showing the steps of the manufacturing method according to the present invention, FIG. 2 is a top view thereof, and FIG. 3 is a schematic cross-sectional view showing the steps of the conventional manufacturing method. 1...n-5i substrate 2-n-GaAs film 3-p
-GaAs film 4--・Au/Zn film 5・AI film 5
=SiN film 7...Heat-resistant glass 8...Au film
Claims (1)
膜をエピタキシャル成長させる半導体素子の製造方法に
おいて、 前記半導体基板上に、前記半導体基板の特 定の結晶方向とその垂直方向とにわたって格子状に、前
記半導体膜の不完全結晶領域を形成する工程と、 前記不完全結晶領域を除く各領域に電極を 形成して熱処理を施す工程と、 形成した各電極を導電性膜にて結線する工 程と を有することを特徴とする半導体素子の製 造方法。[Claims] 1. A method for manufacturing a semiconductor device in which a plurality of layers of semiconductor films of different conductivity types are epitaxially grown on a semiconductor substrate, wherein a specific crystal direction of the semiconductor substrate and its perpendicular direction are formed on the semiconductor substrate. forming imperfectly crystalline regions of the semiconductor film in a lattice shape across directions; forming electrodes in each region excluding the imperfectly crystalline regions and subjecting them to heat treatment; and connecting each of the formed electrodes to a conductive film. 1. A method of manufacturing a semiconductor device, comprising the step of connecting wires.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1085560A JPH02263478A (en) | 1989-04-03 | 1989-04-03 | Manufacture of semiconductor element |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1085560A JPH02263478A (en) | 1989-04-03 | 1989-04-03 | Manufacture of semiconductor element |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH02263478A true JPH02263478A (en) | 1990-10-26 |
Family
ID=13862198
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1085560A Pending JPH02263478A (en) | 1989-04-03 | 1989-04-03 | Manufacture of semiconductor element |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH02263478A (en) |
-
1989
- 1989-04-03 JP JP1085560A patent/JPH02263478A/en active Pending
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