JPS6155782B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a method of manufacturing a semiconductor integrated circuit device. Integrated injection logic circuit devices (hereinafter referred to as “integrated injection logic” circuit devices) are conventional semiconductor integrated circuit devices.
Taking IIL/IC as an example, its manufacturing process is shown in FIGS. 1A to 1F. That is, this
As is generally done in bipolar ICs, IIL-IC first forms an n-type high concentration buried layer 2 on a p-type silicon semiconductor substrate 1, and then forms an n-type low concentration buried layer 2 as shown in FIG. 1A. Grow epitaxial layer 3. Then, as shown in FIG. 1B, an oxide film 10 is formed.
1 and a nitride film 201, which is an oxidation-resistant film, are sequentially formed and patterned into a predetermined shape, and using this as a mask, the epitaxial layer 3 is removed to a predetermined depth, and then ion implantation is performed to prevent channel cuts. Form layer 4. Further, selective oxidation is performed using the nitride film 201 as a mask, and the isolation oxide film 10 is
At the same time, B ⁺ ions are implanted through a part of the thin oxide film 104 using a resist mask, and as shown in FIG. A concentration layer 6 is formed. At this time, the channel cut layer 4 is re-diffused to form a layer 5. Then, as shown in FIG. 1D, B ⁺ ions are implanted through the oxide film 104 using a resist mask in the same manner as described above, and p-type high concentration layers 7 and 8 are formed in the n-type low concentration epitaxial layer 3. After growing a phosphorus glass film 105 on these by CVD method, this phosphorus glass film 105 and p-type low and high concentration layers 6, 7, and 8 are annealed at the same time, and further, as shown in FIG. As shown in E, a window is opened in the p-type low concentration layer 6, and a window is opened in the n-type high concentration layer 9, 10, 11 in the adjacent epitaxial layer 3, and an n-type high concentration layer 12 is formed here. to form. Finally, windows are opened in the p-type heavily doped layers 7 and 8, and electrode wiring is provided for each of the p-type high concentration layers 7 and 8, together with the window openings, to form a p-type emitter, which is the emitter of the pnp transistor.
The injector electrode 401 is placed on the high concentration layer 7, and the pnp
A ground electrode 402 is connected to the n-type high concentration layer 12 for taking out the electrode connected to the epitaxial layer 3 which is the base of the transistor and the emitter of the reverse direction npn transistor, and the ground electrode 402 is connected to the p An input electrode 403 is connected to the p-type high-concentration layer 8 for taking out the electrode connected to the low-concentration layer 6, and an output electrode 40 is connected to the n-type high-concentration layer 9, 10, 11, which is the collector of the reverse operation npn transistor.
4, 405, and 406 are connected as shown in FIG. 1F. And each electrode 404 as the collector,
405 and 406 from the side closer to the base electrode C ₁ ,
Assuming C ₂ and C ₃ , it is generally known that the current amplification factor βu of a reverse operation npn transistor decreases more greatly in the high current range as the collector is farther away from the base electrode, as shown in Figure 2. It is thought that this is because the base resistance increases as the collector is farther away from the base electrode. Also, there is a third difference between the IIL gate propagation delay time tpd and the power consumption pd.
It is known that the power delay characteristic shown in the figure (for example, Semiconductor Transistor Research Group, IEICE Technical Report SSD76-89, P37: High Speed IIL With
Self-Aligned Double Diffusion Injector
[S ² L]). Here, if the base area is the same and the pnp transistor characteristics are the same, (tpd∝βu ^1/2 ) holds true, so as shown in FIG. 3, the farther the collector is from the base electrode, the larger (tpd) becomes. Therefore, the performance of IIL gate ICs manufactured using conventional manufacturing methods has the disadvantage that characteristics differ between the output terminals, and the performance is limited by the slow (tpd) of the output furthest from the base electrode. Furthermore, if the base area (S _B ), the pnp transistor characteristics, and the current amplification factor (βu) are the same,
(tpd∝S _B ) holds true, so to improve its performance, the collector area (S _c ) must be increased as shown in Figure 4.
Although attempts have been made to reduce the base area (S _B ) by making _{the value} smaller, as shown in _FIG .
_B ), this results in a significant decrease in (βu) as shown in FIG. Therefore, as shown in Fig. 7, the minimum (tpd), i.e.,
(tpdmin) becomes ( _S
However , if (S _c ) is reduced beyond a certain value, (β ) becomes faster than the effect of (S _B ).
Due to the effect of the increase in u), the speed suddenly slows down. In other words, the performance of IIL gate ICs manufactured using conventional manufacturing methods is optimal when the collector area is relatively large (approximately 4 times the minimum pattern size) under given design criteria; However, if the gate area is made smaller than this optimum area, the performance deteriorates rapidly, which is a major drawback. Therefore, the purpose of the present invention is to obtain the same large value (βu) between each collector, and also to have a structure in which (S _c /S _B ) is large even with a small collector area (S _c ), and a decrease in (βu) can be prevented. The present invention provides a method of manufacturing a semiconductor integrated circuit device that can improve the integration density. In order to achieve such an object, the present invention provides a step of forming a two-layer insulating film consisting of an oxide film and an oxidation-resistant film on the surface of a semiconductor substrate in which a first conductive layer is selectively formed within a second conductive layer. , a step of oxidizing the surface of this oxidation-resistant film and converting a part of the oxidation-resistant film into an oxide film, and selectively removing this three-layer insulating film to open a plurality of windows in the first conductive layer. a step of forming a polysilicon film doped with a second conductivity type impurity so as to cover the window opening, and a step of forming a second conductive layer within the first conductive layer using the polysilicon film as a diffusion source. After the diffusion formation, a step of patterning the polysilicon film, a step of removing the surface exposed portion of the three-layer insulating film, a step of forming an oxide film on the surface of the patterned polysilicon film, and a step of patterning the three-layer insulating film. a step of sequentially removing an exposed nitride film portion and an exposed inner layer oxide portion of the insulating film; a step of diffusing and forming a first conductive layer between each of the diffusion-formed second conductive layers; This method includes a step of commonly wiring an electrode made of a low-resistance metal on each first conductive layer, and will be described in detail below using examples. FIGS. 8A to 8H are cross-sectional views sequentially illustrating manufacturing steps illustrating an embodiment of the method for manufacturing a semiconductor integrated circuit device according to the present invention. First, as shown in FIG. 8A, an n-type heavily doped buried layer 2 is formed on a p-type silicon semiconductor substrate 1, and then an n-type lightly doped epitaxial layer 3 is grown. Then, as shown in FIG. 8B, the oxide film 10 is
1 and a nitride film 201, which is an oxidation-resistant film, are sequentially formed and patterned into a predetermined shape. Using these as a mask, the epitaxial layer 3 is removed to a predetermined depth, and then ion implantation is performed to prevent channel cuts. Form layer 4. Further, the nitride film 20
1 as a mask, selective oxidation is performed to form an isolation oxide film 103 and a part of the thin oxide film 10.
B ⁺ ions are implanted using a resist mask through 4 to selectively form a p-type lightly doped layer 6 in the n-type lightly doped epitaxial layer 3, as shown in FIG. 8C. At this time, the channel cut layer 4 is re-diffused to form a layer 5. Then, as shown in FIG. 8D, a nitride film 202 is deposited on the p-type low concentration layer 6 as an oxidation-resistant film. Next, nitride film 2
The surface of 02 is oxidized to form an oxide film 115.
Then, as shown in FIG. 8E, a layer corresponding to FIG. After opening windows, depositing a polysilicon film on the upper layer including each of these window openings and diffusing n-type high concentration impurities, or depositing the doped polysilicon film, Using a polysilicon film doped as a diffusion source, the n-type high concentration layers 9, 10, 11 as collectors and the n-type high concentration layer 12 for taking out the electrodes are formed, and this polysilicon film is patterned. Each membrane 30
1, 304, 305, 306 and 302 are obtained. In the steps shown in FIGS. 8D and 8E, the oxide film 104 is used for washing out the base electrode extraction region, and the nitride film 104 is
02 are each made thinner to about 500 to 1000 Å due to distortion, and the oxide film 115 is made thinner to 50 to 100 Å, and the polysilicon film is patterned by gas (CF ₄ + O ₂ ) plasma etching using the resist as a mask. Furthermore, each film 304, 305, 306 and 302 substantially serves as a diffusion source for each layer 9, 10, 11 and 12.
The film 301 is used as a mask to leave the base layer of the pnp transistor. Here, the reason why the nitride film 202 is oxidized to form a very thin oxide film 115 is that if the oxide film between the polysilicon film and the nitride film is thick, the polysilicon film is selectively oxidized as shown in FIG. When the polysilicon film is deposited, the edges of the polysilicon film swell up, causing disconnection of the electrode wiring.
This is because if 05 is formed by CVD, the thickness is limited to about 1000 Å at most, and there is a risk of the above-mentioned wire breakage. Nitride films are originally used as oxidation-resistant films, and their oxidation rate is very slow, making them very suitable for forming thin oxide films. In other words, it converts into an oxide film with a thickness of about 70 Å in 3 hours of wet oxidation at 950°C. Furthermore, as a stopper during patterning of the polysilicon film, the thin oxide film can sufficiently serve as a stopper as long as extreme overetching is not performed. Next, as shown in FIG. 8F, the membranes 301 and 30
4, 305, 306 and 302, each oxide film 106 to 110 as an interlayer insulating film is formed at a thickness of 5,000 yen each.
The exposed portion of the nitride film 202 is etched away, and the exposed portion of the oxide film 104 is washed out, as shown in FIG. 8G. Similarly,
P-type high concentration layer 7 and each n-type high concentration layer 9, 10, 11
A p-type high concentration layer 8 for taking out the base electrode is formed by diffusion in between, and finally, as shown in FIG. A common base electrode 403
are each made of a low-resistance metal such as aluminum, and each of the polysilicon films serves as a corresponding electrode. Here, in order to describe the effects of this embodiment configuration, IIL inverter gate (fanout 3) patterns according to the conventional method and this embodiment method are created using the same design standards as shown in FIGS. 9 to 11. Indicated. In these figures, the standard dimension a is 2 μm
It is. Figure 9 shows the case where optimal performance is obtained using the conventional method, and the dimensional data in this case is gate area =
56μm×16μm=896μm ² , (S _c )=6μm×6μ
m = 36μm ² , (S _B ) = 46μm x 16μm (on the drawing)
45μm×13μm=585μm ² , (S _c /S _B )=
It is 0.0615. Figure 10 shows the case of designing with this embodiment method with the same collector area (S _c ) as the conventional method, and similarly, gate area = 51 μm × 12 μm.
m=612μm ² , (S _c )=6μm×6μm=36μm ² ,
(S _B ) = 42μm x 12μm (on the drawing) 41μm x 9
μm=369 μm ² , (S _c /S _B )=0.0976, and the gate area is reduced to about 2/3. FIG. 11 shows a case where this embodiment method is designed so that (S _c /S _B ) is almost the same as the conventional method, and similarly,
Gate area = 45μm x 10μm = 450μm ² , (S _c ) =
4μm×4μm=16μm ² , (S _B )=35μm×10μ
m (on the drawing) 34 μm x 7 μm = 238 μm ² , (S
_c / S _B ) = 0.0672, and the performance comparison at this time is shown in the following table.

[Table] In addition, in this embodiment method, unlike the conventional method, in order to reduce the base resistance, the p
No need for high concentration layer A, base area (S _B )
As shown in Fig. 4, it is less than half of the conventional value, and therefore (S _c /S _B ) is also improved to about twice that of the conventional value, as shown in Fig. 5. (βu) also increases significantly, as shown in FIG. Furthermore, the base resistance (r' _BB ) is almost the same for (C ₁ ) and (C ₃ ), and is less than 1/2 for (C ₁ ) and less than 1/10 for (C ₃ ) compared to the conventional one. becomes very small. And the (βu) value is (C ₁ ),
(C ₃ ) has almost the same value, and (C ₃ ) has approximately 1.5 times the conventional value, and due to the reduction in the base area and the increase in (βu), (tpd min) is lower than the conventional value. Compared to (C ₁ ), the speed is 52% faster and (C ₃ ) is 45% faster, and the same (tpd min) is obtained for (C ₁ ) and (C ₃ ) as shown in FIG. Furthermore, in this example,
Even when the collector area (S _c ) is made smaller to the minimum pattern size, (βu) is obtained at 10 or more, and there is no sudden drop in performance as in the conventional case. It goes without saying that the present invention can also be applied to SITL in which the IIL inverter transistor is replaced with an SIT (Static Induction Transistor). As described above in detail, according to the method of manufacturing a semiconductor integrated circuit device according to the present invention, a base electrode is provided between each collector, and electrode wiring is made of a low resistance metal, thereby making it possible to The same size (βu) can _be obtained with
However, (S _c /S _B ) is large, it is possible to prevent a decrease in (βu), there is no difference in performance between output terminals, and a significant improvement can be expected, and the integration density can be improved without deteriorating performance. There are effects such as being able to.

[Brief explanation of the drawing]

FIGS. 1A to 1F are cross-sectional views sequentially showing the manufacturing steps of a conventional method for manufacturing a semiconductor integrated circuit device, and FIGS. 2 to 7 compare the conventional method and the method of an embodiment of the present invention. 8A to 8H are cross-sectional views sequentially showing the manufacturing steps of an embodiment of the method for manufacturing a semiconductor integrated circuit device according to the present invention, and FIGS. 9 to 11. are each pattern diagram showing a comparison between the conventional method and the method according to an embodiment of the present invention.
FIG. 2 is a diagram for explaining the case where the oxide film between the polysilicon film and the nitride film in FIGS. 8A to 8H is thick. DESCRIPTION OF SYMBOLS 1...p-type semiconductor substrate, 2...n-type high concentration buried layer, 3...n-type low concentration epitaxial layer, 4...
... channel cut prevention layer, 5 ... rediffused layer, 6 ... p-type low concentration layer, 7 and 8 ... p-type high concentration layer, 9, 10, 11 and 12 ... n-type high concentration layer, 101... Oxide film, 103... Isolation oxide film, 104... Thin oxide film, 105... Phosphorous glass film, 106-110... Oxide film, 115... Oxide film, 201... Nitride film, 301, 302 ,30
4, 305 and 306...polysilicon film, 4
01... Injector electrode, 403... Base electrode, 404, 405 and 406... Output electrode. Note that in the figures, the same elements are given the same numbers.

Claims (1)

[Claims] 1. A step of forming a two-layer insulating film consisting of an oxide film and an oxidation-resistant film on the surface of a semiconductor substrate on which a first conductive layer is selectively formed within a second conductive layer, and oxidizing the surface of this oxidation-resistant film. , a step of converting a part of the oxidation-resistant film into an oxide film, a step of selectively removing the three-layer insulating film to form a plurality of windows in the first conductive layer, and covering the window openings. forming a polysilicon film into which impurities of a second conductivity type are introduced, and forming a second conductive layer within the first conductive layer using this polysilicon film as a diffusion source, and then patterning the polysilicon film. a step of removing an exposed surface portion of the three-layer insulating film, a step of forming an oxide film on the surface of the patterned polysilicon film, and an exposed portion of the nitride film and an inner layer oxide film of the three-layer insulating film. a step of sequentially removing the exposed portions, a step of diffusing and forming a first conductive layer between each of the second conductive layers formed by diffusion, and a step of forming a first conductive layer with a low resistance metal on each of the first conductive layers formed by diffusion. 1. A method of manufacturing a semiconductor integrated circuit device, comprising the step of common wiring of electrodes.