JPS6155773B2 - - Google Patents

Info

Publication number
JPS6155773B2
JPS6155773B2 JP54092581A JP9258179A JPS6155773B2 JP S6155773 B2 JPS6155773 B2 JP S6155773B2 JP 54092581 A JP54092581 A JP 54092581A JP 9258179 A JP9258179 A JP 9258179A JP S6155773 B2 JPS6155773 B2 JP S6155773B2
Authority
JP
Japan
Prior art keywords
die pad
wiring layer
light emitting
dry film
emitting diode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP54092581A
Other languages
English (en)
Other versions
JPS5618480A (en
Inventor
Osamu Ichikawa
Tetsuo Sadamasa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP9258179A priority Critical patent/JPS5618480A/ja
Publication of JPS5618480A publication Critical patent/JPS5618480A/ja
Publication of JPS6155773B2 publication Critical patent/JPS6155773B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Led Device Packages (AREA)
  • Wire Bonding (AREA)
  • Die Bonding (AREA)

Description

【発明の詳細な説明】 この発明は発光ダイオード（LED）を用いた
デイスプレイ装置の製造方法に関する。
デイスプレイ装置には液晶、プラズマ、エレク
トロルミネツセンス、LED等を用いたものがあ
り、電子計算機等から出た電気信号を可視光に変
換して機械から人間への情報伝達をなすものであ
る。
ここで用いる用語“デイスプレイ”又は“表
示”は一単位光源（１ドツド）又は複数ドツドが
同一平面上に配置され光源あるいは所望のパタン
を表示するように動作するものであり、特に複数
ドツドが用いられて英数字や漢字のパタン又は特
殊な記号を含むパタン、絵やグラフイツクなどの
連続的パタンを作り出すにはドツド間隔を出来る
だけ接近して配置し個々のドツドへ選択的な電気
信号を送り駆動する方法が一般的に採用される。
更にくわしくのべると、この電気信号はその駆動
回路により高速に操作されるので個々のドツドは
極めて短かいパルスで一時的に駆動され発光する
ものであつても人間の目に残像性質があるのでく
り返し信号を送ることによつて静止した画像や文
字に見えるものである。更に従来この種のデイス
プレイ装置の有用性を高めるため同一平面上に配
置された１ドツド又は複数ドツドから多色の光を
発光する仕組みをもたせて同時間表示の中でより
多くの情報をもたらすことの出来るデイスプレイ
装置が望まれこの要求を解決する手段として特に
LEDを用いたデイスプレイは応答速度や明るさ
の点、更に多色表示が可能であるなどが上記した
他の方式に比べ優れているので近年かなり有望視
され始めた。しかしながらLEDを用いたデイス
プレイ装置の製造作業は基板上に載置するLED
ペレツトの数や密度が増すにつれて困難度が急増
してしまい例えば第１図や第２図に示すような欠
点が生じた。すなわち図面を用いて説明すれば第
１図に於いて絶縁基板（図示せず）上にx1，x2…
の行となる第１の金属配線層１２ａ，１２ｂを形
成しこの上から基板上に中間の絶縁層（図示せ
ず）を第１の金属配線１２ａ，１２ｂの所定部に
開孔１０１ａ，１０２ａ，１０３ａ，１０１ｂ，
１０２ｂ，１０３ｂ、して設け中間絶縁層を介し
てy1，y2，y3の列を構成する第２の金属配線１４
ａ，１４ｂ，１４ｃ，１４ｄ，１４ｅ，１４ｆが
形成される。次に開孔１０１ａ，１０２ａ，１０
３ａ，１０１ｈ，１０２ｂ，１０２ｃ、のそれぞ
れに適量の銀ペーストを滴下しおよそ5800Åのピ
ーク波長を発光する第１のLEDペレツト１５１
Ga，１５２Ga，１５３Ga，１５１Gb，１５２
Gb，１５３Gbと、およそ7000Åのピーク波長を
発光する第２のLEDペレツト１５１Ra，１５２
Ra，１５３Ra，１５１Rb，１５２Rb，１５３
Rbとを開孔におのおの単数ずつ載置する。しか
しながら載置されたLEDペレツトはｘ軸とｙ軸
との交点を中心にして例えばx1とy1で交わる開孔
内のLEDペレツト１５１Gaおよび１５１RGの如
く交点を中心に双方のペレツト間隔をおよそ50ミ
クロンの幅をもつて載置するのが正しいが他の開
孔内のLEDペレツト配置は中心からずれたりペ
レツトが回転したりしているので字や絵をデイス
プレイしたとき明るさく形のバランスがくずれて
しまう欠点を生じた。
又、第２図では第１の金属配線層２２の所定部
にペレツト２６ａ，２６ｂ，２６ｃを落し込む
際、更に各々のLEDペレツトの位置を修整する
際に押し上げられたり、はみ出したりする銀ペー
スト２５が中間の絶縁層２３上に設けられた第２
の金属配線層２４へ接触してダイオードマトリツ
クアレイの配線シヨート２０１および２０２を発
生させた。
更に従来このような欠点を補うためダイパツド
部に滴下する銀ペーストの量をへらして行なえば
マウント強度が低下しワイヤボンデイングの際に
ペレツトがはがれてしまう結果をまねいた。
本発明はこのような欠点を解決するに鑑みなさ
れたもので、あらかじめLED搭載基板のダイパ
ツド部を除く基板全域にドライフイルム系のホト
レジストを形成しておき、熱硬化性導電性接着剤
の塗布、ペレツトの位置合せを行なうことによつ
て従来起つた位置合せ不良や配線間の短絡をなく
すことが出来る方法を提供するものである。
以下本発明の実施例を第３図ａ〜ｆを用いて説
明する。
第３図ａ〜ｆを順追つて説明すればアルミナ等
のセラミツク基板３１上に厚膜印刷技術に依りお
よそ20ミクロンの第１の金属配線層３２を形成す
る。次に、LEDペレツトを載置するダイパツド
部分を除く基板表面上に印刷し焼成しておよそ50
ミクロンの絶縁層３３を形成する。更に所望のパ
タンとなるおよそ10ミクロンの第２の金属配線層
３４を印刷して形成する（第３図ａ）。
次に、上記基板表面一体にドライフイルムのホ
トレジスト例えばデユポン社のリストンをおよそ
90℃、１Kg／cm2の条件をもつラミネータによりは
り付け、写真技術によりダイエレ部分の上記ホト
レジスト膜を除去し、所望の開孔パタンをもつド
ライフイルム３９を形成する（第３図ｂ）。
次に導電性熱硬化性接着剤例えば銀ペースト３
５をドライフイルムの開孔されたダイパツド部分
へ0.005〜0.02mg程度滴下する（第３図ｃ）。
次に銀ペーストが形成されたダイパツドへ例え
ば縦0.3mm、横0.3mm、高さ0.3mmの大きさのLED
ペレツト３６ａ，３６ｂをドライフイルム開孔を
補助として落し込み位置合せする。そして約150
℃のオーブンで約60分の熱処理を施こす（第３図
ｄ）。
次に所定のLEDペレツトをマウントし熱処理
を施こした基板を有機溶剤例えばジクロルメタン
に浸しドライフイルムを剥離する。そしてトリク
レンやアルコール、アセトン等を用いて基板表面
上の洗浄を行なう（第３図ｅ）。
最後にボンデイング装置でおよそ50ミクロンの
Auワイヤ３８でLEDペレツト上のアノード電極
３７ａ，３７ｂと第２の金属配線層３４へ接続ボ
ンデイングをする（第３図ｆ）。
以上のべた製造方法によれば製造上の不良を極
めて少なくすることが可能となり従つて低値で歩
留りを向上させることができペレツトの数が多く
なるにつれてその効果は大きい。
なお上記実施例のダイパツド部に導電性ペース
トを塗布する方法は、個々のダイパツド部へ適量
のペーストを滴下することにかぎらず、上記した
ドライフイルム表面上一体に導電性ペーストを塗
布しスキージで基板表面を押すように印刷で行な
つても良い。
またドライフイルム開孔の大きさは、LEDペ
レツトの大きさよりもやや大きい寸法であること
が望ましく、上記ペレツトの大きさ（0.3mm、0.3
mm、0.3mm）にあつては、フイルムの厚さ50〜100
ミクロンで長さ幅とも0.35〜0.4mmが適当であ
る。
さらに、１ドツド内に複数個のLEDペレツト
を載置する場合にはペレツトの配置に応じて長さ
幅を変えるがペレツトの大きさより0.05〜0.1mm
程度大きい面積の開孔がよい。
【図面の簡単な説明】
第１図および第２図は従来方法における欠点を
説明するための平面図および断面図、第３図ａ〜
ｆは本発明における製造方法の一実施例を説明す
るための工程断面図である。 ２１，３１……絶縁基板、２２，３２，１２
ａ，１２ｂ……第１の金属配線層、１０１ａ，１
０１ｂ，１０２ａ，１０２ｂ，１０３ａ，１０３
ｂ……絶縁層の開孔、１５１Ga，１５１Gb，１
５２Ga，１５２Gb，１５３Ga，１５３Gb……第
１のピーク波長をもつ発光ダイオード、１５１
Ra，１５１Rb，１５２Ra，１５２Rb，１５３
Ra，１５３Rb……第２のピーク波長をもつ発光
ダイオード、２４，３４，１４ａ，１４ｂ，１４
ｃ，１４ｄ，１４ｅ，１４ｆ……第２の金属配線
層、２５，３５……導電性熱硬化性接着剤、２６
ａ，２６ｂ，２６ｃ，３６ａ，３６ｂ……発光ダ
イオードペレツト、２７ａ，２７ｂ，２７ｃ，３
７ａ，３７ｂ……ペレツト上の電極、２８，３８
……Auワイヤ、３９……ドライフイルム系フオ
トレジスト、２０１，２０２……銀ペーストによ
る配線間シヨートの欠陥部。

Claims (1)

  1. 【特許請求の範囲】 １ 絶縁基板上に第１の金属配線層を形成、この
    第１の金属配線層の所定部にダイパツドを設けこ
    のダイパツド部上に単数又は複数の発光ダイオー
    ドペレツトを載置固定して一発光単位となるドツ
    ドを形成し、このドツドを同一平面上に行および
    列状に複数個配置してなる発光ダイオード型のデ
    イスプレイ装置の製造方法において、 (1) 前記第１の金属配線層のダイパツド部を除き
    第２の金属配線層を含む基板全域にドライフイ
    ルム系のフオトレジスト膜を形成する工程と、 (2) ダイパツド部の個々に熱硬化性導電接着剤を
    塗布する工程と、 (3) 前記導電接着材が塗布されたダイパツド部に
    発光ダイオードペレツトを載置しドライフイル
    ム―フオトレジスト開孔の側壁に沿つて発光ダ
    イオードペレツトの位置を合せる工程と、 (4) 120〜160℃の温度で熱処理し前記導電接着剤
    を硬化しダイパツド部に載置された発光ダイオ
    ードペレツトを機械的および電気的に接続する
    工程と、 (5) 前記ドライフイルム系のフオトレジスト膜を
    除去する工程と、 (6) 前記発光ダイオードペレツトの電極と、前記
    第１の金属配線層上に絶縁層を介して設けられ
    た前記第２の金属配線層とをワイヤボンデイン
    グ接続する工程とからなるデイスプレイ装置の
    製造方法。
JP9258179A 1979-07-23 1979-07-23 Manufacture of display device Granted JPS5618480A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9258179A JPS5618480A (en) 1979-07-23 1979-07-23 Manufacture of display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9258179A JPS5618480A (en) 1979-07-23 1979-07-23 Manufacture of display device

Publications (2)

Publication Number Publication Date
JPS5618480A JPS5618480A (en) 1981-02-21
JPS6155773B2 true JPS6155773B2 (ja) 1986-11-29

Family

ID=14058389

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9258179A Granted JPS5618480A (en) 1979-07-23 1979-07-23 Manufacture of display device

Country Status (1)

Country Link
JP (1) JPS5618480A (ja)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5844726A (ja) * 1981-09-11 1983-03-15 Nippon Telegr & Teleph Corp <Ntt> ゲッタリング方法
JP2531636B2 (ja) * 1986-08-18 1996-09-04 ロ−ム株式会社 サ−マルヘツド
JP3736001B2 (ja) * 1996-02-29 2006-01-18 株式会社デンソー 電子部品の実装方法

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51126068A (en) * 1975-04-25 1976-11-02 Hitachi Ltd Manufacturing method of semi-conductor equipment

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51126068A (en) * 1975-04-25 1976-11-02 Hitachi Ltd Manufacturing method of semi-conductor equipment

Also Published As

Publication number Publication date
JPS5618480A (en) 1981-02-21

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