JPS615560A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS615560A JPS615560A JP59127879A JP12787984A JPS615560A JP S615560 A JPS615560 A JP S615560A JP 59127879 A JP59127879 A JP 59127879A JP 12787984 A JP12787984 A JP 12787984A JP S615560 A JPS615560 A JP S615560A
- Authority
- JP
- Japan
- Prior art keywords
- foil
- aluminum
- electrode
- chip
- terminals
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 39
- 239000011347 resin Substances 0.000 claims abstract description 15
- 229920005989 resin Polymers 0.000 claims abstract description 15
- 229910052782 aluminium Inorganic materials 0.000 claims description 44
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 42
- 229910052802 copper Inorganic materials 0.000 claims description 34
- 239000010949 copper Substances 0.000 claims description 34
- 239000010409 thin film Substances 0.000 claims description 21
- 239000011810 insulating material Substances 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 4
- 230000002093 peripheral effect Effects 0.000 claims 1
- 238000007789 sealing Methods 0.000 abstract description 11
- 239000000853 adhesive Substances 0.000 abstract description 3
- 238000000034 method Methods 0.000 abstract description 3
- 239000011888 foil Substances 0.000 abstract 5
- 230000000717 retained effect Effects 0.000 abstract 1
- 229910000679 solder Inorganic materials 0.000 description 12
- 239000000758 substrate Substances 0.000 description 7
- 238000005476 soldering Methods 0.000 description 6
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 238000005245 sintering Methods 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000009740 moulding (composite fabrication) Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/142—Metallic substrates having insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Manufacturing & Machinery (AREA)
- Materials Engineering (AREA)
- Ceramic Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明は、電力半導体モジュールなどに使用する半導
体装置の改良に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to improvements in semiconductor devices used in power semiconductor modules and the like.
〔従来技術〕〜
近年、電子機器の発達は著しく、その小形軽量化が急速
に進んでいる。これらの基をなすものは、半導体装置の
小形化および信頼性の向上によるものである。このなか
でも特にトランジスタの大電流容量化に伴って、かかる
半導体装置の中容量の電力用半導体装置への応用が活発
になっており、小形軽量化を図ったパワーモジュールの
分野への適用も多（なってきている。[Prior Art] In recent years, electronic devices have made remarkable progress and are rapidly becoming smaller and lighter. These advances are based on the miniaturization and improved reliability of semiconductor devices. Among these, in particular, with the increase in the current capacity of transistors, the application of such semiconductor devices to medium-capacity power semiconductor devices has become active, and there are also many applications in the field of power modules that aim to reduce size and weight. (It has become to.
このようなパワーモジュールのｉ長は軽量化と低価格で
あるが、このためには装置は樹脂封止形となる。パワー
モジュールでは、複数個の半導体チップを組込んでおり
、半導体チップ自体も大電流容量化に伴い大きくなるた
め、外形寸法は従来の樹脂封止形半導体装置に比べ、か
なり大きなものとなる。最近では、６素子入りのパワー
モジ、エールも実用化されている。The i-length of such a power module is light in weight and low in price, but to achieve this, the device must be of a resin-sealed type. A power module incorporates a plurality of semiconductor chips, and the semiconductor chips themselves become larger as the current capacity increases, so the external dimensions are considerably larger than those of conventional resin-sealed semiconductor devices. Recently, a power module with 6 elements, Ale, has also been put into practical use.
このようなことから、パワーモジュールの樹脂封止には
、従来のものとは異なった構造が必要となってくる。な
かでも最も問題となるのは、外形寸法が大きくなること
により、容器内に充てんされる樹脂の体積が大きくなり
、半導体チップの発熱による温度上昇により、封止樹脂
の膨張や温度低下時における収縮によるひずみがチップ
やアルミニウム線に加わり、チップの割れやアルミニウ
ム線の断□線の原因となることである。For this reason, resin sealing of power modules requires a structure different from conventional ones. The biggest problem among these is that as the external dimensions increase, the volume of the resin filled in the container increases, and the temperature rise due to the heat generated by the semiconductor chip causes the sealing resin to expand and contract when the temperature drops. The resulting strain is applied to the chip and aluminum wire, causing cracks in the chip and breaks in the aluminum wire.
これらを防止するため、最近では、容器内部の下層には
絶縁材としてのゲル状軟質樹脂で封止してチップやアル
ミニウム線部を囲み、上層には充てん後硬化することに
より強度の方が高くなる封止樹脂で封止し、引出された
外部端子の保持とモジュールの機械的保護とを行う二重
の樹脂封止構造のものが増えてきた。In order to prevent this, recently the lower layer inside the container is sealed with a gel-like soft resin as an insulating material to surround the chip and aluminum wires, and the upper layer is filled and hardened to have higher strength. There has been an increase in the number of double resin-sealed structures that hold external terminals pulled out and mechanically protect the module.
この種の従来の半導体装置を第１図に示す。第２図は第
１図の平面図であり、第３図は第２図の要部を拡大して
示す断面図である。これらの図はパワーモジュールに使
用するトランジスタの場合を示し、図において、■はア
ルミニウム放熱板であり、１上面にアルミナ材等からな
る絶縁基板２が固着されている。この絶縁基板２上には
内部端子としてのペース電極３Ｂ、コレクタ電極３Ｃ，
エミッタ電極３Ｅが纏着されている。コレクタ電極３Ｃ
上には、トランジスタチップ４１．フライホイールダイ
オードチップ４０が、ペース電極３Ｂ上には、スピード
アンプダイオードチップ４２が固着されている。また、
ベース電極３Ｂは、外部端子１４に、エミッタ電極３Ｅ
は外部端子１５に引出されている。トランジスタチップ
４１上面のペースポンディングパッドがスピードアンプ
ダイオードチップ４２上面のパッドとアルミニウム線２
０Ｂにより、フライホイールダイオードチップ４０上面
のエミッタポンディングパッドが対応するエミッタ電極
３Ｅとアルミニウム線２０Ｂにより、さらにトランジス
タ干ツブ４１上面のエミッタボンケイングパッドが対応
するエミッタ電極１（図示せず）とアルミニウム線２１
Ｅによりそれぞれボンディング接続されでいる。A conventional semiconductor device of this type is shown in FIG. 2 is a plan view of FIG. 1, and FIG. 3 is an enlarged cross-sectional view of the main part of FIG. 2. These figures show the case of a transistor used in a power module. In the figures, ▪ is an aluminum heat sink, and an insulating substrate 2 made of alumina material or the like is fixed to the upper surface of the plate. On this insulating substrate 2, a pace electrode 3B as an internal terminal, a collector electrode 3C,
An emitter electrode 3E is attached. Collector electrode 3C
On top is a transistor chip 41. A flywheel diode chip 40 and a speed amplifier diode chip 42 are fixed on the pace electrode 3B. Also,
The base electrode 3B is connected to the external terminal 14, and the emitter electrode 3E
is drawn out to the external terminal 15. The pace bonding pad on the top surface of the transistor chip 41 is connected to the pad on the top surface of the speed amplifier diode chip 42 and the aluminum wire 2.
0B, the emitter bonding pad on the top surface of the flywheel diode chip 40 is connected to the corresponding emitter electrode 3E and the aluminum wire 20B, and the emitter bonding pad on the top surface of the transistor block 41 is connected to the corresponding emitter electrode 1 (not shown). aluminum wire 21
They are bonded and connected by E.
次に、上記従来装置の組立て方法につしζて説明する。Next, a method of assembling the above-mentioned conventional device will be explained in detail.
・
まず、絶縁基板２の両面の所要ハンダ付＋ｉ箇所にメタ
ライズ層を施す、放熱板１上にハンダ扉片２／ｌ−介し
て絶縁基板２を形成し、その上にそれぞれハンダ薄片３
Ａ″を介してベース電株３Ｂ″、□コレクタ電極３Ｃ，
エミッタ電極３Ｅを載せる。さらにベース電極３Ｂ上に
ハンダ薄片４Ａを介してスピードアップダイオードチッ
プ４２を、コレクタ電極３Ｃ上にハンダ薄片４Ａを介し
てトランジスタチップ４１．フライホイールダイ・オー
ドチップ４０を配置する。- First, a metallized layer is applied to the required soldering+i locations on both sides of the insulating substrate 2.The insulating substrate 2 is formed on the heat sink 1 through the solder door piece 2/l-, and then the solder thin piece 3 is placed on each of the insulating substrate 2.
Base electrode 3B'', □Collector electrode 3C,
Place the emitter electrode 3E. Further, a speed-up diode chip 42 is placed on the base electrode 3B via a thin solder piece 4A, and a transistor chip 41 is placed on the collector electrode 3C via a thin solder piece 4A. A flywheel diode chip 40 is placed.
このように、各部品が載せられた放熱板１を組立設備の
図示しない熱板上に載せ、加熱し′を各部品をハンダ融
着する。次にトランジスタチップ４１上面のエミッタポ
ンディングパッドとエミッタ電極（図示せず）とをアル
ミニウム線２１Ｂにより、フライホイールダイオードチ
ップ４０上面のエミッタポンディングパッドとエミッタ
電極３Ｅとをアルミニウム線２０Ｈにより、さらにミ
トランジスタチップ４１上面のペースポンディングパッ
ドとベース電極３Ｂ上のスピードアップダイオードチッ
プ４２の上面のパッドとをアルミニウム線２０Ｂにより
ライ十ボンドする。各電極３Ｂ。In this way, the heat sink 1 on which each component is mounted is placed on a hot plate (not shown) of an assembly facility, heated, and the components are soldered together. Next, the emitter bonding pad on the top surface of the transistor chip 41 and the emitter electrode (not shown) are connected with an aluminum wire 21B, and the emitter bonding pad on the top surface of the flywheel diode chip 40 and the emitter electrode 3E are connected with an aluminum wire 20H.
The pace bonding pad on the upper surface of the transistor chip 41 and the pad on the upper surface of the speed-up diode chip 42 on the base electrode 3B are bonded to each other by an aluminum wire 20B. Each electrode 3B.
３Ｇ、３Ｅの先端を上方に曲げ起こし、これを各電極の
外部端子９〜１５にはんだ付は等により接続する。次い
で、放熱板１上に外装容′ＩＳ５を接着剤等で接着し、
外装容器５内部の下層には絶縁材としてのゲル状封止樹
脂で封止し、外装容器５の上層には各外部端子９〜１５
固定のための硬化封止樹脂７で封止して製品が完成する
。The tips of 3G and 3E are bent upward and connected to the external terminals 9 to 15 of each electrode by soldering or the like. Next, the outer package 'IS5 is glued onto the heat sink 1 with adhesive or the like.
The lower layer inside the outer container 5 is sealed with gel-like sealing resin as an insulating material, and the upper layer of the outer container 5 is provided with external terminals 9 to 15.
The product is completed by sealing with a hardened sealing resin 7 for fixing.
ところで、上記従来の半導体装置は、放熱板１上にハン
ダ薄片２Ａを介して絶縁基板２を、さらにこの上にそれ
ぞれハンダ薄片３Ａを介してベース電極３Ｂ、コレクタ
電極３Ｃ，エミッタ電極３Ｅを載せなければならず、ま
た、各トランジスタＴｒＬ Ｔｒ２．Ｔｒ３のコレクタ
電極３Ｃの先端を外部端子９に銅の電極１６を介してハ
ンダ接続しなければならず、そして、各トランジスタＴ
ｒ４． Ｔｒ５＋ Ｔ−ｒ６のエミッター極３Ｅの先端
、を銅の電極１７を介して外部端子１０にハンダ接続し
なければならず、トランジスタＴｒｉのエミッタ電極３
ＥとトランジスタＴｒ４のコレクタ電極３Ｃとを外部端
子１）に、トランジスタＴｒ２のエミッタ電極３Ｅとト
ランジスタＴｒ５のコレクタ電極３Ｃとを外部端子１２
に、トランジスタＴｒ３のエミッタ電極３Ｅとトランジ
スタＴｒ６のコレクタ電極３Ｃとを外部端子１３に、そ
れぞれ立体的にハンダ接続し、トランジスタＴｒｉ〜Ｔ
ｒ６のベース電極３Ｂとエミッタ電極３Ｅとは外部端子
１４．１５に、それぞれハンダ付けをしなければならず
、ハンダ付けに非常に多くの組立工数を必要とし、外部
端子９〜１５の位置決めが非常に困難であり、位置決め
のための外部端子９〜１５の位置儒正に多くの作業時間
がかかる等の欠点があった。Incidentally, in the conventional semiconductor device described above, the insulating substrate 2 must be placed on the heat sink 1 through the solder thin piece 2A, and the base electrode 3B, collector electrode 3C, and emitter electrode 3E must be placed on top of this through the solder thin piece 3A, respectively. In addition, each transistor TrL Tr2 . The tip of the collector electrode 3C of the Tr 3 must be soldered to the external terminal 9 via the copper electrode 16, and each transistor T
r4. The tip of the emitter electrode 3E of Tr5 + T-r6 must be soldered to the external terminal 10 via the copper electrode 17, and the emitter electrode 3 of the transistor Tri
E and the collector electrode 3C of the transistor Tr4 are connected to the external terminal 1), and the emitter electrode 3E of the transistor Tr2 and the collector electrode 3C of the transistor Tr5 are connected to the external terminal 12.
Then, the emitter electrode 3E of the transistor Tr3 and the collector electrode 3C of the transistor Tr6 are three-dimensionally soldered to the external terminal 13, respectively, and the transistors Tri to T
The base electrode 3B and emitter electrode 3E of r6 must be soldered to the external terminals 14 and 15, respectively, and the soldering requires a large number of assembly steps, and the positioning of the external terminals 9 to 15 is very difficult. It is difficult to locate the external terminals 9 to 15, and it takes a lot of time to properly position the external terminals 9 to 15.
この発明は、上記のような従来のものの欠点を解消する
ためになされたもので、アルミニウム放熱板上全面に絶
縁層を直接焼結等により形成し、その上に全面に銅薄及
びアルミニウム薄を形成したのち、パターンニング及び
エツチングにより所望部分のみに銅薄、アルミニウム薄
を残し、これらの上に半導体チップ及びその外部電極端
子を直接載せ、直接ボンディングを行なうようにするこ
とにより、内部電極端子をな（してハンダ付は箇所を大
幅に減らすことができる半導体装置を提供することを目
的としている。This invention was made in order to eliminate the drawbacks of the conventional ones as described above. An insulating layer is formed on the entire surface of an aluminum heat sink by direct sintering, etc., and then a thin copper layer and a thin aluminum layer are formed on the entire surface of the insulating layer. After forming, patterning and etching are performed to leave a thin layer of copper and aluminum only in the desired areas, and the semiconductor chip and its external electrode terminals are placed directly on top of these, and internal electrode terminals are directly bonded. The purpose of this is to provide a semiconductor device in which the number of soldering points can be significantly reduced.
以下、この発明の実施例を図について説明する。 Embodiments of the present invention will be described below with reference to the drawings.
第４〜第６図はこの発明の一実施例による半導体装置を
示すもので、第４図はぞのパワートランジスタモジュー
ルの斜視図であり、第５図は第４図の平面図、第６図は
第５図の要部を拡大して示す断面図である。これらの図
において、第１図〜第３図と同一符号は同−又は相当部
分を示し、第６図において、２２は軽量なアルミニウム
放熱板 （１上の全面に形成された絶縁
層、６Ｃは該絶縁層２２上に形成された銅薄、４はこの
銅薄６Ｃ上にハンダ３Ａにより固着された、銅又はＭｏ
板８等にハンダ付け（４Ａ）した半導体チップ、６Ｂ。4 to 6 show a semiconductor device according to an embodiment of the present invention, where FIG. 4 is a perspective view of the power transistor module, FIG. 5 is a plan view of FIG. 4, and FIG. 6 is a perspective view of the power transistor module. 5 is an enlarged cross-sectional view of the main part of FIG. 5. FIG. In these figures, the same reference numerals as in Figures 1 to 3 indicate the same or equivalent parts. In Figure 6, 22 is a lightweight aluminum heat sink (an insulating layer formed on the entire surface of The copper thin film 4 formed on the insulating layer 22 is copper or Mo, which is fixed on the copper thin film 6C with solder 3A.
Semiconductor chip 6B soldered to board 8 (4A).
６Ｅはそれぞれ絶縁層２２上に形成された銅薄、７Ｂ、
７Ｂは該各銅薄６Ｂ、６Ｅ上に形成されたアルミニウム
薄である。一方第５図において、絶縁層２２上に銅薄Ｅ
ｉＢ、’６Ｅが形成され、銅薄６Ｂ上にベース電極１４
．スピードアップダイオードチップ４３が固着され、か
つアルミニウムＩ！７Ｂが形成されており、一方、銅薄
６Ｅ上にエミッタ電極１５が固着され、かつアルミニウ
ム薄７Ｅが形成されている。チップ４のエミッタ電極は
銅薄上に形成されたアルミニウム薄１９の配線により外
部端子１０に接続されている。6E is a thin copper layer formed on the insulating layer 22, 7B,
7B is an aluminum thin film formed on each of the copper thin films 6B and 6E. On the other hand, in FIG.
iB, '6E are formed, and the base electrode 14 is formed on the copper thin layer 6B.
．． A speed-up diode chip 43 is fixed and aluminum I! On the other hand, an emitter electrode 15 is fixed on a copper thin layer 6E, and an aluminum thin layer 7E is formed. The emitter electrode of the chip 4 is connected to an external terminal 10 by a thin aluminum wire 19 formed on a thin copper layer.
次に、上記半導体装置の組立て方法について説明する。Next, a method for assembling the above semiconductor device will be explained.
第４． ５． ６図に示すごとく、アルミニウム放熱板
ｌ上の片面全面に絶縁層２２を直接焼結によ′り形成し
、その上の全面に銅薄を、該銅薄上全面にア）レミニウ
ム薄を形成し、それら銅薄及びアルミニウム薄をパター
ンニングしたのち、エツチングによりそれらの不必要部
分を取り除いて、チップ４．４３及びその端子１４．１
５のハンダ付けすべき部分に銅薄６Ｂ、６Ｇ、６Ｅを残
し、かつ残りの端子９〜１３のハンダ付は部及びアルミ
ニウム薄１８．１９により配線を行うべき部分にも銅薄
を残し、アルミニウムボンディングを行うべき部分にア
ルミニウム薄７Ｂ、７Ｅを、配線を行うべき部分にアル
ミニウム薄１８．１９を残す。4th. 5. As shown in Figure 6, an insulating layer 22 is formed on the entire surface of one side of the aluminum heat sink l by direct sintering, a copper thin layer is formed on the entire surface of the insulating layer 22, and a) reminium thin layer is formed on the entire surface of the copper thin layer. After patterning the copper thin film and the aluminum thin film, unnecessary parts thereof are removed by etching to form the chip 4.43 and its terminals 14.1.
5, leave copper thin films 6B, 6G, and 6E on the parts to be soldered, and leave copper thin films on the parts to be soldered with the remaining terminals 9 to 13 and aluminum thin films 18 and 19 in the parts where wiring should be done. Aluminum thin sheets 7B and 7E are left in the areas where bonding is to be performed, and aluminum thin sheets 18 and 19 are left in the areas where wiring is to be performed.
このようにして形成された銅薄上のハンダ付けすべき所
に金属マスク等によりクリーム状のハンダ３Ａをハンダ
印刷する。続いて例えば銅薄６Ｃ上に、銅又はＭｏ板８
等をハンダ付けしたチップ４を載せ、一方他の銅薄上に
端子９〜１５を載せ、リフロー炉かホットプレート上で
ハンダ３Ａの融点以上に加熱し、チップ４を銅薄６Ｃに
、端子９〜１５を他の銅薄にそれぞれハンダ付けする。Cream-like solder 3A is solder-printed using a metal mask or the like on the thus formed copper thin film at the locations to be soldered. Next, for example, a copper or Mo plate 8 is placed on the thin copper 6C.
etc. are soldered thereon, and terminals 9 to 15 are placed on another copper thin layer, heated to a temperature higher than the melting point of solder 3A in a reflow oven or on a hot plate, and the chip 4 is soldered onto the copper thin layer 6C. Solder ~15 to other copper thin pieces.
その後、チップ４のベースおよびエミッタの各ポンディ
ングパッドと、対応するベース電極１４．工ミッタ電極
１５の先端のアルミニウム薄７Ｂ、７Ｅとをそれぞれア
ルミニウム線３０Ｂ、３０ｇでボンディング接続する。Thereafter, each of the base and emitter bonding pads of the chip 4 and the corresponding base electrode 14. The thin aluminum sheets 7B and 7E at the tip of the transmitter electrode 15 are connected by bonding with aluminum wires 30B and 30g, respectively.
次に各端子９〜１５をハンダ付けした根元より起こして
立てる。次にアルミニウム放熱板１上に外装容器５を接
着剤等で接着し、外装容器５内部の下層には絶縁材とし
てのゲル状封止樹脂で封止し、外装容器５の上層には。Next, raise each terminal 9 to 15 from the soldered base. Next, the outer container 5 is bonded onto the aluminum heat sink 1 with an adhesive or the like, the lower layer inside the outer container 5 is sealed with a gel-like sealing resin as an insulating material, and the upper layer of the outer container 5 is sealed.
各外部端子９〜１５を固定するための硬化封止樹脂７で
封止して製品が完成する。The product is completed by sealing with a hardened sealing resin 7 for fixing each external terminal 9 to 15.
このように本実施例の半導体装置では、アルミニウム放
熱板１上全面に形成された絶縁層２２上の所要部分のみ
に＃Ｉｉｌ薄を残し、その１部の銅薄上に直接外部端子
９〜１５をハンダ付けしているため、従来のように内部
の端子と外部端子をハンダ付けする必要はない。また、
アルミニウム放熱板１上の全面に絶縁層２２を形成した
ので、トランジスタＴｒｉ〜Ｔｒ６を絶縁するために個
々に絶縁基板２を放熱板１上にハンダ付けする必要はな
い。In this way, in the semiconductor device of this embodiment, the #Iil thin layer is left only in the required portions on the insulating layer 22 formed on the entire surface of the aluminum heat sink 1, and the external terminals 9 to 15 are directly placed on a portion of the copper thin layer. Since it is soldered, there is no need to solder the internal and external terminals as in the conventional case. Also,
Since the insulating layer 22 is formed on the entire surface of the aluminum heat sink 1, there is no need to individually solder the insulating substrate 2 onto the heat sink 1 in order to insulate the transistors Tri to Tr6.
また、外部端子９．１０はこれを絶縁層２２上の一部の
銅薄上に設け、それぞれコレクタ電極、エミッタ電極と
アルミニウム１）８．１９の配線により直接平面配線し
ているため、従来のように立体配線とならずハンダ付は
箇所が減少しており、これは外部端子１）〜１３につい
ても同様である。In addition, the external terminals 9 and 10 are provided on a part of the copper thin layer on the insulating layer 22, and the collector electrode, the emitter electrode, and the aluminum 1) 8, 19 wiring are directly connected on a plane, so that the conventional As shown in the figure, the number of soldering points is reduced instead of three-dimensional wiring, and the same is true for external terminals 1) to 13.
さらに、外部端子９〜１５の位置決めも容易である等、
大幅に作業時間を短縮できる等の利点を有する。Furthermore, positioning of the external terminals 9 to 15 is easy, etc.
It has the advantage of being able to significantly shorten working time.
以上のように、この発明によれば、アルミニウム放熱板
上全面に絶縁層を形成し、その上に全面に銅薄及びアル
ミ、ニウム薄を形成したのち、バターンニング及びエツ
チングにより所望部分のみに銅薄、アルミニウム薄を残
し、これらの上に半導体チップ、その外部電極端子を載
せ、あるいはポンディングを行うことにより、内部電極
端子をなくしてアルミニウム放熱板上に直接外部電極端
子を設げ、これを平面配線できるようにしたので、大幅
にハンダ付は箇所を減らし、作業時間を短縮できる効果
がある。As described above, according to the present invention, an insulating layer is formed on the entire surface of an aluminum heat sink, a thin copper layer and a thin layer of aluminum and nickel are formed on the entire surface of the insulating layer, and then copper is etched only in desired areas by patterning and etching. By leaving a thin aluminum layer and placing the semiconductor chip and its external electrode terminals on these, or by bonding, the internal electrode terminals are eliminated and the external electrode terminals are directly placed on the aluminum heat sink. Planar wiring is now possible, which greatly reduces the number of soldering points and reduces work time.
４、ＦＩ！Ｊカ。工４、 （第
１図、第２図は従来の半導体装置を示す斜視図と平面図
、第３図はその装置の要部を拡大して示す断面図、第４
図、第５図はこの発明の一実施例による半導体装置の斜
視図及び平面図、第６図、は本実施例装置の要部を拡大
し王示す断面図であ１・・・アルミニウム放熱板、２ｉ
・・・絶縁層、４・・・半導体チップ、４３・・・スぐ
−ドアツブダイオードチップ、５・・・外装容器、６Ｂ
、もＣ，６Ｅ・・・銅薄、７Ｂ、７Ｅ、１８．１９・・
・アルミニウム薄、３０Ｂ、３０Ｅ・・・アルミニウム
線（ポンディングワイヤ）、７・・・硬化封止樹脂（外
部呻子固定のための樹脂）、９〜１５・・・外部端子。4.FI! Jka. 4. (Figures 1 and 2 are a perspective view and a plan view showing a conventional semiconductor device, Figure 3 is a sectional view showing an enlarged view of the main parts of the device, and Figure 4
5 is a perspective view and a plan view of a semiconductor device according to an embodiment of the present invention, and FIG. 6 is an enlarged cross-sectional view showing the main parts of the device of this embodiment. 1. Aluminum heat sink , 2i
...Insulating layer, 4...Semiconductor chip, 43...Sugu-door tube diode chip, 5...Outer container, 6B
, also C, 6E... copper thin, 7B, 7E, 18.19...
- Aluminum thin, 30B, 30E...Aluminum wire (ponding wire), 7...Hardened sealing resin (resin for external fixation), 9-15...External terminal.
なお図中同一符号は同−又は相当部分を示す。Note that the same reference numerals in the figures indicate the same or equivalent parts.
Claims (1)
縁層と、該絶縁層上の全面に銅薄を形成し該銅薄上の全
面にアルミニウム薄を形成したのち、半導体チップ又は
該チップの各電極の外部端子を固着する部分を形成する
銅薄、アルミニウムボンディングを行う部分を形成する
アルミニウム薄及び平面配線のためのアルミニウム薄が
残るようにパターンニング及びエッチングにより上記銅
薄、アルミニウム薄の不必要部分を取り除いて形成され
た複数の銅薄及び複数のアルミニウム薄と、上記一部の
銅薄上に固着された半導体チップと、上記他の一部の銅
薄上に固着された上記チップの各電極の外部端子と、上
記半導体チップと上記アルミニウム薄とを接続するボン
ディングワイヤと、上記アルミニウム放熱板上の周縁部
にその内部下層に絶縁材としての樹脂を、その上層に上
記外部端子固定のための樹脂を封止して装着された絶縁
材からなる外装容器とを備えたことを特徴とする半導体
装置。(1) After forming an insulating layer on the entire surface of one side of an aluminum heat sink, forming a copper thin film on the entire surface of the insulating layer, and forming an aluminum thin film on the entire surface of the copper thin film, a semiconductor chip or the chip is formed. Patterning and etching are performed so that the copper thin film forming the part for fixing the external terminal of each electrode, the aluminum thin film forming the aluminum bonding part, and the aluminum thin film for planar wiring remain. A plurality of copper thin films and a plurality of aluminum thin films formed by removing necessary parts, a semiconductor chip fixed on some of the copper thin films, and the above chip fixed on the other part of the copper thin films. A bonding wire connecting the external terminal of each electrode, the semiconductor chip and the aluminum thin film, a resin as an insulating material on the inner lower layer on the peripheral edge of the aluminum heat sink, and a resin as an insulating material on the upper layer for fixing the external terminal. 1. A semiconductor device comprising: an outer container made of an insulating material sealed with a resin for storage.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59127879A JPS615560A (en) | 1984-06-19 | 1984-06-19 | Semiconductor device |
| KR1019850002517A KR900001744B1 (en) | 1984-06-19 | 1985-04-15 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59127879A JPS615560A (en) | 1984-06-19 | 1984-06-19 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS615560A true JPS615560A (en) | 1986-01-11 |
Family
ID=14970896
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59127879A Pending JPS615560A (en) | 1984-06-19 | 1984-06-19 | Semiconductor device |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPS615560A (en) |
| KR (1) | KR900001744B1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1255298A3 (en) * | 2001-05-04 | 2005-04-06 | Ixys Corporation | Power device with a plastic molded package and direct bonded substrate |
-
1984
- 1984-06-19 JP JP59127879A patent/JPS615560A/en active Pending
-
1985
- 1985-04-15 KR KR1019850002517A patent/KR900001744B1/en not_active IP Right Cessation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1255298A3 (en) * | 2001-05-04 | 2005-04-06 | Ixys Corporation | Power device with a plastic molded package and direct bonded substrate |
Also Published As
| Publication number | Publication date |
|---|---|
| KR860000714A (en) | 1986-01-30 |
| KR900001744B1 (en) | 1990-03-19 |
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