JPS6154555A - Buffer control system - Google Patents

Abstract

PURPOSE:To cope with a high data input/output speed of a channel processor by providing a 2-stage register corresponding to each channel between a register of each channel and a common buffer memory and setting the data width of the 2-stage register at the value equal to the word width of each access of the buffer memory. CONSTITUTION:For data input, the 1-byte data received by a register 3 is transferred by a control part 12 to the sequential byte position of a register 10. The dta on the register 10 is transferred to a register 11 every byte through a control part 13 serving as the 1st common transfer mechanism. When four bytes are transferred to the register 11, the 4-byte data of the register 11 is written on a buffer memory 6 through a control part 14 serving as the 2nd common transfer mechanism. For data output, the 4-byte data is read out of the memory 6 by the part 14 and transferred to the register 11. Then the part 13 transfers the data every byte to the register 10, and the part 12 sets this data every byte to the register 3 from the register 10.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a channel processing device of a 1FF processing system, and particularly relates to a channel processing device for a 1FF processing system, and in particular, data between a buffer storage device that holds input/output data of the channel processing device and each channel. This invention relates to a buffer control method for controlling transfer.

Peripheral devices or input/output devices of an information processing system are connected to channels, and a device configured to control a plurality of such channels and connect with a central processing unit and a main storage device is called a channel processing device or the like.

A channel processing device may be provided with a common buffer storage device for a plurality of channels as a storage function for buffering data input/output between each channel and a main storage device during a transfer process.

[Conventional technology]

FIG. 2 shows the buffer description 1. 1 is a schematic diagram of a channel processing device having an α device;

The data transferred between the input/output devices of each channel through the data transfer lines 1 and 2 usually has a data width of about 1 to 2 hides, so depending on the width, for example, the data is stored in the 1-byte register 3. Set output data and send it to transfer line 1, or receive manual data from transfer line 2.

In the receiving operation, when data is received in the register 3, it is transferred to the register 4, and the register 3 is placed in a state for receiving the next data.

When the received data is sent to the register 4, a transfer request signal is issued to the buffer control unit 5.
corresponds to the data in register 4,
The process of storing data in the device 6 is started.

The buffer storage device 6 is normally used for main storage access 4'.
! The access unit is composed of a word with a data width that takes into account the - place, etc., and has a data width of about 4 to 8 bytes, so the buffer control unit 5 reads one word from the buffer storage device 6 and receives the received data. Place it at an appropriate bite position and occupy it.

For channels outputting data, register 3
When the next data is sent to the transfer line 1, the next data to be sent is transferred from the register 4 to the register 3. At that point, a transfer request signal is issued to the buffer control unit 5.

The buffer control unit 5 reads the corresponding data word from the buffer storage device 6 and sets one byte therein in the requested register 4.

[Problem that the invention seeks to solve]

According to the above-mentioned conventional method, the buffer storage device 6 must be accessed every time, for example, one byte is transmitted or received on each channel. Therefore, as the number of channels increases, the size of the access load on the buffer storage device 6 becomes a problem. come.

In order to reduce this load, there is a method of increasing the hide width of register 3.4 in the above method, but is it possible to control each channel? JJ'l(There is a problem that it becomes C.

In addition, the channel service by the buffer control unit 5 is a method of randomly processing requests generated from each channel, but this method has been adopted in recent years to cope with the increase in data input/output speed of peripheral devices. For the continuous transfer method of data byte strings, the processing capacity of the buffer storage device 6 and buffer control unit 5 must be set to a capacity with sufficient margin compared to the average required processing capacity. There is a problem in that it increases the chances of loss or retransmission.

[Failure to solve the problem]

The problem described above is that in a channel processing device that includes a secondary channel and a common buffer storage device that holds data to be input/output by the channel, there is a first and second registers provided correspondingly and having the same data width as the data width of the access unit of the buffer storage device;
a first common transfer mechanism that performs data transfer between the register and the second register with a transfer data width equal to the input/output data in ip, and a transfer mechanism between the second register and the buffer storage device; a second common transfer mechanism that executes data transfer between accesses and data widths of the buffer storage device in units of access ii first data width, and the first and second common transfer mechanisms are each fixedly allocated to each channel. 2. The system of the present invention is configured to process the data transfer for the channel at the specified timing. 1
This problem can be solved by one method.

[Effect]

That is, a two-stage register corresponding to each channel is provided between the register 3 of each channel and the common buffer storage device 6, and the data width of the register is set to the word width of the access unit of the buffer storage device 6. Make equal.

In this way, between register 3 and the first register,
The data width between the first register and the second register is the same as that of register 3, for example, 1 hide, and the data width between the second register and the buffer is 1. Transfer with the α device 6 is performed using the access width of the storage device.

By performing each transfer using a time-sharing control method with fixed timing, the data output performance of the buffer storage device 6 can be fully utilized. It can be realized.

〔Example〕

FIG. 1 is a block diagram that does not show the configuration of a portion corresponding to one channel in an embodiment of the present invention.

In this example, the unit of data transfer between the input/output device via the transfer line 1.2 is 1 byte, and the word width of the access unit in the buffer storage device 6 is 1 hide.

Based on this premise, the first register 10 and the second register 11 have a width of 4 hides.

In the data input operation, the control unit 12 transfers 1-byte data received in the register 3 to sequential byte positions in the register 10, and the control unit 13, which is the first common transfer mechanism, transfers the data in the register 10 one byte at a time. At the timing when 4 bytes are transferred to the register 11, the control unit 14, which is the second common transfer mechanism, writes the 4 high 1 to data of the register 11 to the buffer memory 1σ device 6. In the electric data output operation, when the control section 14 reads 4 hide data from the buffer memory unit 6 and transfers it to the register II, the control section 13 transfers it to the register 10 one hide at a time, and the control section 12 transfers it to the register II. 10
The data bytes are sent out by loading the register 3 one hide at a time.

The control unit 15 is a part that controls data transfer between the input/output device and the register 3 using the transfer wire 1 or 2 in each channel.

The control units 12, 13, and 14 are control units common to the channels, and sequentially control data transfer of each channel in a time-sharing manner at timings as illustrated below.

For example, the control sections 12 and 13 are provided in common for 4 channels, the control section 14 is provided in common for 16 channels, and the buffer storage device 6 is provided in common for 6 channels, as shown in FIG. (Data output to bl, (C1
shows the control timing for data input operation.

These figures show only the 4 channels that share a specific set of control units 12 and 13 among the 16 channels mentioned above, and the bold lines indicate each control; It shows. The numbers on the thick line indicate the number of the channel (0 to 3 in this case) that is served at that timing.

Note that the operation timing of the control unit 14 is different from 11a.
The timing for servicing channel numbers 5 to 15, which are channels under the control of the J a11 unit 12.13, is also indicated by dashed lines.

As is clear from these timing diagrams, the method of fixedly assigning timing to each channel eliminates the need to control conflicting service requests, and as shown in the operation of the control unit 14, the buffer storage device 6 Performance can be fully utilized.

Note that the reason why the register 10 has the same 4-hide width as the register 11 is due to the phase shift between the data transfer operation on the transfer line 1 or 2 and the buffer control timing of each part mentioned above (for example, in the input operation, the controller 14 (The timing phase relationship is such that only 3 hides are transferred to register 1 at the time when data in register 11 is to be written.)
This is to cover.

〔Effect of the invention〕

As is clear from the above description, the present invention has a significant industrial effect in that a buffer control force formula that can cope with high-speed data output of a channel processing device can be realized economically.

[Brief explanation of the drawing]

FIG. 1(a) is a block diagram of the configuration of one embodiment of the present invention.
FIGS. (b) and (C) are timing diagrams of an embodiment of the present invention, and FIG. 2 is a block diagram showing an example of a conventional configuration. In the figure, 1.2 is a data transfer key 5), 3.4 is a register, 5 is a buffer control unit, 6 is a buffer recording device, and 10 is a first
11 is a second register, and 12 to 15 are control units. Agent: Patent attorney: Compensation: Koshibu Award I @ Lead) Kaya 1 Figure ζ-fA)

Claims (1)

[Claims] In a channel processing device having a plurality of channels and a common buffer storage device for holding data input/output by the channels, a common buffer storage device is provided between the channels and the buffer storage device corresponding to each channel, first and second registers having the same data width as the data width of the access unit of the buffer storage device;
a first common transfer mechanism that executes data transfer between the register and the buffer storage device in units of a transfer data width equal to the input/output data; and a first common transfer mechanism that transfers data between the second register and the buffer storage device. It has a second common transfer mechanism that executes the access unit data width of the storage device as a unit, and the first and second common transfer mechanisms each perform the above-mentioned transfer for each channel at a timing fixedly assigned to each channel. A buffer control method configured to handle data transfer.